Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38062403

1

T1

16

T2

3746

T3

23476

full_word

48761454

1

T1

5

T2

6217

T3

36921

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	86823577	1			T1	21		T2	9963		T3	60397
auto[TlIntgErrCmd]	76	1			T46	5		T47	3		T103	1
auto[TlIntgErrData]	104	1			T46	6		T47	10		T103	4
auto[TlIntgErrBoth]	100	1			T46	9		T47	7		T103	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46756419

1

T1

1

T2

7041

T3

40747

auto[1]

40067438

1

T1

20

T2

2922

T3

19650

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23430862	1			T1	1		T2	2343		T3	13863
auto[TlIntgErrNone]	partial	auto[1]	14631284	1			T1	15		T2	1403		T3	9613
auto[TlIntgErrNone]	full_word	auto[0]	23325440	1			T2	4698		T3	26884		T4	36086
auto[TlIntgErrNone]	full_word	auto[1]	25435991	1			T1	5		T2	1519		T3	10037
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T46	3		T47	2		T137	2
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T46	2		T47	1		T103	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T163	1		T164	1		T160	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T165	1		T161	1		T166	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T46	2		T47	5		T103	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T46	4		T47	5		T103	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T103	1		T167	1		T161	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T167	1		T163	1		T168	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T46	6		T47	3		T137	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T46	3		T47	3		T103	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T47	1		T158	1		T169	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T169	1		T167	1		T161	1