Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	537382878	56056	0	0
RunThenComplete_M	537382878	706026	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	537382878	56056	0	0
T2	22349	12	0	0
T3	421369	50	0	0
T4	584001	79	0	0
T5	4640	0	0	0
T14	868240	150	0	0
T15	307511	117	0	0
T16	20580	2	0	0
T17	391620	186	0	0
T18	850741	337	0	0
T19	0	135	0	0
T20	0	20	0	0
T21	1762	0	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	537382878	706026	0	0
T2	22349	59	0	0
T3	421369	292	0	0
T4	584001	426	0	0
T5	4640	0	0	0
T14	868240	726	0	0
T15	307511	584	0	0
T16	20580	6	0	0
T17	391620	472	0	0
T18	850741	507	0	0
T19	0	4809	0	0
T20	0	60	0	0
T21	1762	0	0	0