Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	98.55	92.86		100.00	92.00	88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	94.46	98.55	92.86		100.00	92.00	88.89

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	98.55	92.86		100.00	92.00	88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.80	98.75	92.86	100.00	100.00	92.31	90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		69	68	98.55
CONT_ASSIGN	153	1	1	100.00
ALWAYS	161	3	3	100.00
ALWAYS	166	30	30	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
ALWAYS	268	6	5	83.33
CONT_ASSIGN	287	1	1	100.00
ALWAYS	307	6	6	100.00
ALWAYS	338	6	6	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
ALWAYS	420	6	6	100.00
CONT_ASSIGN	431	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
153	1	1
161	3	3
166	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
176	1	1
178	1	1
180	1	1
181	1	1
183	1	1
190	1	1
191	1	1
193	1	1
194	1	1
196	1	1
197	1	1
199	1	1
201	1	1
207	1	1
208	1	1
210	1	1
212	1	1
217	1	1
218	1	1
220	1	1
226	1	1
227	1	1
240	1	1
241	1	1
			MISSING_ELSE
251	1	1
252	1	1
253	1	1
254	1	1
258	1	1
260	1	1
265	1	1
268	1	1
269	1	1
270	1	1
271	0	1
272	1	1
274	1	1
			MISSING_ELSE
287	1	1
307	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
372	1	1
394	1	1
420	1	1
421	1	1
422	1	1
423	1	1
424	1	1
425	1	1
431	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       180
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       207
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       252
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       253
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       254
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       258
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       260
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       265
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       270
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       394
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       431
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	181	Covered	T2,T3,T4
StKmacFlush	208	Covered	T2,T3,T4
StKmacIdle	183	Covered	T1,T2,T3
StKmacMsg	194	Covered	T2,T3,T4
StTerminalError	241	Covered	T5,T6,T7

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	194	Covered	T2,T3,T4
StKey->StTerminalError	241	Covered	T6,T54,T9
StKmacFlush->StKmacIdle	218	Covered	T2,T3,T4
StKmacFlush->StTerminalError	241	Covered	T51,T87
StKmacIdle->StKey	181	Covered	T2,T3,T4
StKmacIdle->StTerminalError	241	Covered	T5,T11,T33
StKmacMsg->StKmacFlush	208	Covered	T2,T3,T4
StKmacMsg->StTerminalError	241	Covered	T7,T8,T88

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		50	46	92.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	253	2	2	100.00
TERNARY	254	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	2	2	100.00
TERNARY	265	2	2	100.00
IF	161	2	2	100.00
CASE	178	10	10	100.00
IF	240	2	2	100.00
IF	268	4	3	75.00
CASE	307	6	5	83.33
CASE	420	6	5	83.33
CASE	338	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (st)
-2-:	180	if ((kmac_en_i && start_i))
-3-:	193	if (sent_blocksize)
-4-:	207	if ((process_i || process_latched))
-5-:	217	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T2,T3,T4
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T2,T3,T4
StKey	-	0	-	-	Covered	T2,T3,T4
StKmacMsg	-	-	1	-	Covered	T2,T3,T4
StKmacMsg	-	-	0	-	Covered	T2,T3,T4
StKmacFlush	-	-	-	1	Covered	T2,T3,T4
StKmacFlush	-	-	-	0	Covered	T2,T3,T4
StTerminalError	-	-	-	-	Covered	T5,T6,T7
default	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	240	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((!rst_ni))
-2-:	270	if ((process_i && (!process_o)))
-3-:	272	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T2,T14,T15
Key256	Covered	T2,T3,T4
Key384	Covered	T2,T14,T15
Key512	Covered	T2,T14,T15
default	Not Covered

	LineNo.	Expression
-1-:	420	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T4,T14,T17
L256	Covered	T1,T2,T3
L384	Covered	T2,T4,T14
L512	Covered	T3,T17,T19
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T2,T14,T15
Key256	Covered	T2,T3,T4
Key384	Covered	T2,T14,T15
Key512	Covered	T2,T14,T15
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	537382878	7195943	0	0
KeyDataStableWhenValid_M	537382878	302347822	0	0
KeyLengthStableWhenValid_M	537382878	302347822	0	0
KmacEnStable_M	537382878	21503	0	0
MaxKeyLenMatchToKey512_A	655	655	0	0
ModeStable_M	537382878	32693	0	0
ProcessLatchedCleared_A	537382878	0	0	0
StrengthStable_M	537382878	38367	0	0
u_state_regs_A	537382878	537256925	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	537382878	7195943	0	0
T2	22349	427	0	0
T3	421369	2754	0	0
T4	584001	3971	0	0
T5	4640	0	0	0
T14	868240	4712	0	0
T15	307511	3807	0	0
T16	20580	0	0	0
T17	391620	346	0	0
T18	850741	0	0	0
T19	0	60977	0	0
T21	1762	0	0	0
T35	0	3054	0	0
T48	0	477	0	0
T62	0	70	0	0

KeyDataStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	537382878	302347822	0	0
T2	22349	11211	0	0
T3	421369	318002	0	0
T4	584001	403858	0	0
T5	4640	0	0	0
T14	868240	345807	0	0
T15	307511	156451	0	0
T16	20580	0	0	0
T17	391620	181482	0	0
T18	850741	0	0	0
T19	0	409262	0	0
T21	1762	0	0	0
T35	0	115711	0	0
T48	0	58426	0	0
T62	0	25205	0	0

KeyLengthStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	537382878	302347822	0	0
T2	22349	11211	0	0
T3	421369	318002	0	0
T4	584001	403858	0	0
T5	4640	0	0	0
T14	868240	345807	0	0
T15	307511	156451	0	0
T16	20580	0	0	0
T17	391620	181482	0	0
T18	850741	0	0	0
T19	0	409262	0	0
T21	1762	0	0	0
T35	0	115711	0	0
T48	0	58426	0	0
T62	0	25205	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	537382878	21503	0	0
T2	22349	7	0	0
T3	421369	19	0	0
T4	584001	27	0	0
T5	4640	0	0	0
T14	868240	72	0	0
T15	307511	55	0	0
T16	20580	4	0	0
T17	391620	77	0	0
T18	850741	0	0	0
T19	0	51	0	0
T20	0	30	0	0
T21	1762	0	0	0
T48	0	6	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655	655	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	537382878	32693	0	0
T2	22349	18	0	0
T3	421369	20	0	0
T4	584001	29	0	0
T5	4640	1	0	0
T14	868240	167	0	0
T15	307511	136	0	0
T16	20580	4	0	0
T17	391620	80	0	0
T18	850741	1	0	0
T19	0	55	0	0
T21	1762	0	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	537382878	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	537382878	38367	0	0
T1	1461	1	0	0
T2	22349	14	0	0
T3	421369	20	0	0
T4	584001	41	0	0
T14	868240	167	0	0
T15	307511	142	0	0
T16	20580	5	0	0
T17	391620	100	0	0
T18	850741	1	0	0
T21	1762	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	537382878	537256925	0	0
T1	1461	1380	0	0
T2	22349	22289	0	0
T3	421369	421296	0	0
T4	584001	583939	0	0
T14	868240	868183	0	0
T15	307511	307449	0	0
T16	20580	20530	0	0
T17	391620	391568	0	0
T18	850741	850669	0	0
T21	1762	1704	0	0