Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	538828858	5927	0	0
entropy_period_rd_A	538828858	2321	0	0
intr_enable_rd_A	538828858	2980	0	0
prefix_0_rd_A	538828858	2261	0	0
prefix_10_rd_A	538828858	2321	0	0
prefix_1_rd_A	538828858	2378	0	0
prefix_2_rd_A	538828858	2515	0	0
prefix_3_rd_A	538828858	2459	0	0
prefix_4_rd_A	538828858	2260	0	0
prefix_5_rd_A	538828858	2328	0	0
prefix_6_rd_A	538828858	2293	0	0
prefix_7_rd_A	538828858	2250	0	0
prefix_8_rd_A	538828858	2392	0	0
prefix_9_rd_A	538828858	2358	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	5927	0	0
T45	143110	1760	0	0
T46	0	2	0	0
T47	0	2	0	0
T101	0	4	0	0
T102	0	4	0	0
T104	0	1	0	0
T105	0	213	0	0
T106	0	206	0	0
T116	0	1	0	0
T117	0	3	0	0
T118	413081	0	0	0
T119	47919	0	0	0
T120	1481	0	0	0
T121	1308	0	0	0
T122	179050	0	0	0
T123	320282	0	0	0
T124	292406	0	0	0
T125	400972	0	0	0
T126	813393	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2321	0	0
T89	9524	29	0	0
T92	8391	9	0	0
T95	10040	91	0	0
T117	7315	14	0	0
T135	52265	444	0	0
T136	6439	6	0	0
T137	10851	20	0	0
T138	4659	10	0	0
T139	2837	16	0	0
T140	26428	181	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2980	0	0
T89	9524	51	0	0
T92	8391	3	0	0
T98	4467	12	0	0
T105	15136	3	0	0
T117	7315	12	0	0
T135	52265	444	0	0
T136	6439	44	0	0
T141	1092	5	0	0
T142	1989	17	0	0
T143	2446	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2261	0	0
T89	9524	14	0	0
T92	8391	12	0	0
T98	4467	13	0	0
T117	7315	9	0	0
T135	52265	390	0	0
T136	6439	3	0	0
T137	10851	26	0	0
T138	4659	1	0	0
T139	2837	4	0	0
T143	2446	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2321	0	0
T89	9524	16	0	0
T92	8391	2	0	0
T98	4467	4	0	0
T117	7315	1	0	0
T135	52265	401	0	0
T136	6439	29	0	0
T137	10851	9	0	0
T138	4659	7	0	0
T139	2837	1	0	0
T143	2446	9	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2378	0	0
T89	9524	19	0	0
T92	8391	9	0	0
T98	4467	7	0	0
T117	7315	11	0	0
T135	52265	453	0	0
T136	6439	26	0	0
T137	10851	7	0	0
T138	4659	7	0	0
T139	2837	3	0	0
T143	2446	7	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2515	0	0
T89	9524	27	0	0
T92	8391	13	0	0
T95	10040	64	0	0
T98	4467	13	0	0
T117	7315	2	0	0
T135	52265	463	0	0
T136	6439	13	0	0
T137	10851	24	0	0
T138	4659	4	0	0
T139	2837	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2459	0	0
T89	9524	23	0	0
T92	8391	15	0	0
T98	4467	7	0	0
T107	16528	5	0	0
T117	7315	6	0	0
T135	52265	439	0	0
T136	6439	17	0	0
T137	10851	48	0	0
T138	4659	17	0	0
T143	2446	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2260	0	0
T89	9524	16	0	0
T92	8391	10	0	0
T98	4467	2	0	0
T105	15136	1	0	0
T117	7315	4	0	0
T135	52265	378	0	0
T136	6439	13	0	0
T137	10851	35	0	0
T138	4659	3	0	0
T143	2446	7	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2328	0	0
T89	9524	36	0	0
T92	8391	20	0	0
T98	4467	8	0	0
T117	7315	3	0	0
T135	52265	400	0	0
T136	6439	25	0	0
T137	10851	26	0	0
T138	4659	5	0	0
T139	2837	12	0	0
T143	2446	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2293	0	0
T89	9524	35	0	0
T92	8391	23	0	0
T98	4467	15	0	0
T117	7315	14	0	0
T135	52265	390	0	0
T136	6439	9	0	0
T137	10851	24	0	0
T138	4659	5	0	0
T139	2837	19	0	0
T143	2446	6	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2250	0	0
T89	9524	23	0	0
T92	8391	14	0	0
T98	4467	8	0	0
T117	7315	11	0	0
T135	52265	458	0	0
T136	6439	25	0	0
T137	10851	20	0	0
T138	4659	7	0	0
T139	2837	15	0	0
T143	2446	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2392	0	0
T89	9524	29	0	0
T92	8391	13	0	0
T98	4467	12	0	0
T117	7315	14	0	0
T135	52265	432	0	0
T136	6439	30	0	0
T137	10851	29	0	0
T138	4659	7	0	0
T139	2837	8	0	0
T143	2446	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538828858	2358	0	0
T89	9524	27	0	0
T92	8391	12	0	0
T98	4467	16	0	0
T117	7315	6	0	0
T135	52265	452	0	0
T136	6439	27	0	0
T137	10851	23	0	0
T138	4659	7	0	0
T139	2837	8	0	0
T143	2446	9	0	0