Group : kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg
Group Instance : AppKeymgr_cg_(1)
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance AppKeymgr_cg_(1)
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
3 |
0 |
3 |
100.00 |
Variables for Group Instance AppKeymgr_cg_(1)
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
sw_configured_hash_mode |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : AppLc_cg_(1)
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance AppLc_cg_(1)
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
3 |
0 |
3 |
100.00 |
Variables for Group Instance AppLc_cg_(1)
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
sw_configured_hash_mode |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : AppRom_cg_(1)
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance AppRom_cg_(1)
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
3 |
0 |
3 |
100.00 |
Variables for Group Instance AppRom_cg_(1)
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
sw_configured_hash_mode |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable sw_configured_hash_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for sw_configured_hash_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
cshake |
1012 |
1 |
|
|
T13 |
2 |
|
T22 |
1 |
|
T36 |
2 |
shake |
980 |
1 |
|
|
T13 |
7 |
|
T22 |
2 |
|
T36 |
2 |
sha3 |
1063 |
1 |
|
|
T13 |
4 |
|
T21 |
2 |
|
T36 |
3 |
Summary for Variable sw_configured_hash_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for sw_configured_hash_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
cshake |
537 |
1 |
|
|
T13 |
1 |
|
T22 |
1 |
|
T46 |
7 |
shake |
522 |
1 |
|
|
T13 |
2 |
|
T21 |
1 |
|
T46 |
9 |
sha3 |
513 |
1 |
|
|
T13 |
1 |
|
T46 |
10 |
|
T52 |
5 |
Summary for Variable sw_configured_hash_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for sw_configured_hash_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
cshake |
488 |
1 |
|
|
T13 |
2 |
|
T21 |
3 |
|
T46 |
8 |
shake |
520 |
1 |
|
|
T13 |
2 |
|
T22 |
1 |
|
T46 |
6 |
sha3 |
533 |
1 |
|
|
T21 |
1 |
|
T36 |
1 |
|
T46 |
5 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |