Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43691378

1

T1

26192

T2

225

T3

159

full_word

51745407

1

T1

42519

T2

430

T3

435

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	95436475	1			T1	68711		T2	655		T3	594
auto[TlIntgErrCmd]	102	1			T108	4		T109	3		T110	4
auto[TlIntgErrData]	114	1			T108	10		T109	2		T110	3
auto[TlIntgErrBoth]	94	1			T108	6		T109	5		T110	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51615979

1

T1

45658

T2

339

T3

307

auto[1]

43820806

1

T1

23053

T2

316

T3

287

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26828616	1			T1	16074		T2	114		T3	96
auto[TlIntgErrNone]	partial	auto[1]	16862486	1			T1	10118		T2	111		T3	63
auto[TlIntgErrNone]	full_word	auto[0]	24787215	1			T1	29584		T2	225		T3	211
auto[TlIntgErrNone]	full_word	auto[1]	26958158	1			T1	12935		T2	205		T3	224
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T108	1		T109	1		T167	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T108	3		T109	2		T110	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T144	1		T168	2		T173	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T170	2		T174	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T108	1		T109	1		T110	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T108	6		T109	1		T110	2
auto[TlIntgErrData]	full_word	auto[0]	10	1			T108	3		T176	1		T168	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T168	1		T175	1		T171	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T108	2		T109	2		T110	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T108	3		T109	3		T110	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T108	1		T173	1		T171	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T166	1		T177	1		T175	1