Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39968532	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

49600096

1

T1

431

T2

439

T3

162

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48600240	1			T1	329		T2	309		T3	83
values[0x0]	19846616	1			T1	150		T2	139		T3	53
values[0x1]	21121772	1			T1	157		T2	147		T3	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31010603	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

58558025

1

T1

483

T2

473

T3

171

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	341609	1			T1	3		T4	8		T12	5
valid_sources[0x01]	414976	1			T2	11		T12	16		T13	17
valid_sources[0x02]	292701	1			T1	1		T12	4		T13	19
valid_sources[0x03]	1483597	1			T1	1		T3	3		T4	3
valid_sources[0x04]	288756	1			T3	6		T12	6		T13	40
valid_sources[0x05]	289480	1			T1	1		T2	4		T4	2
valid_sources[0x06]	288371	1			T1	3		T2	3		T12	22
valid_sources[0x07]	288419	1			T1	2		T2	2		T3	1
valid_sources[0x08]	312943	1			T1	1		T4	2		T12	15
valid_sources[0x09]	311865	1			T1	2		T2	1		T12	4
valid_sources[0x0a]	322784	1			T1	9		T3	2		T4	3
valid_sources[0x0b]	287701	1			T3	1		T12	13		T13	26
valid_sources[0x0c]	328648	1			T1	2		T2	5		T12	15
valid_sources[0x0d]	288827	1			T1	3		T2	9		T12	7
valid_sources[0x0e]	304234	1			T1	1		T2	2		T12	12
valid_sources[0x0f]	1119351	1			T1	2		T2	2		T12	28
valid_sources[0x10]	327238	1			T2	5		T12	2		T13	42
valid_sources[0x11]	284790	1			T4	3		T12	10		T13	54
valid_sources[0x12]	288990	1			T2	5		T12	8		T13	5
valid_sources[0x13]	519491	1			T2	6		T4	1		T12	14
valid_sources[0x14]	285990	1			T1	1		T2	3		T4	3
valid_sources[0x15]	289263	1			T1	9		T12	18		T13	44
valid_sources[0x16]	304797	1			T2	7		T12	10		T13	24
valid_sources[0x17]	284736	1			T1	2		T12	28		T13	45
valid_sources[0x18]	284222	1			T1	6		T4	1		T12	16
valid_sources[0x19]	286443	1			T1	1		T4	4		T12	17
valid_sources[0x1a]	311975	1			T1	2		T12	4		T13	55
valid_sources[0x1b]	290817	1			T1	3		T12	15		T13	42
valid_sources[0x1c]	289076	1			T1	7		T2	5		T3	5
valid_sources[0x1d]	286081	1			T1	4		T12	18		T13	68
valid_sources[0x1e]	299515	1			T1	2		T2	5		T12	4
valid_sources[0x1f]	1453246	1			T1	2		T3	3		T12	15
valid_sources[0x20]	286049	1			T1	5		T3	1		T12	24
valid_sources[0x21]	287174	1			T2	1		T3	2		T12	2
valid_sources[0x22]	287428	1			T1	3		T2	4		T12	11
valid_sources[0x23]	290291	1			T1	2		T2	3		T12	15
valid_sources[0x24]	286236	1			T1	3		T2	1		T12	7
valid_sources[0x25]	620359	1			T1	1		T3	8		T12	1
valid_sources[0x26]	286336	1			T1	1		T2	8		T12	11
valid_sources[0x27]	285041	1			T1	2		T2	5		T3	1
valid_sources[0x28]	287502	1			T1	3		T2	7		T4	2
valid_sources[0x29]	286641	1			T1	2		T2	5		T3	1
valid_sources[0x2a]	288415	1			T1	6		T2	4		T12	14
valid_sources[0x2b]	287739	1			T1	1		T2	6		T12	3
valid_sources[0x2c]	286659	1			T1	3		T12	5		T13	20
valid_sources[0x2d]	285523	1			T1	7		T2	9		T12	5
valid_sources[0x2e]	298837	1			T1	5		T12	5		T13	49
valid_sources[0x2f]	286151	1			T2	2		T4	5		T12	4
valid_sources[0x30]	315526	1			T1	1		T4	1		T12	8
valid_sources[0x31]	1277851	1			T1	7		T12	8		T13	58
valid_sources[0x32]	289550	1			T3	5		T12	4		T13	17
valid_sources[0x33]	313694	1			T1	7		T12	12		T13	18
valid_sources[0x34]	288064	1			T1	1		T2	4		T4	6
valid_sources[0x35]	284900	1			T1	4		T12	6		T13	34
valid_sources[0x36]	408932	1			T2	2		T12	9		T13	31
valid_sources[0x37]	289086	1			T1	2		T12	14		T13	38
valid_sources[0x38]	286170	1			T12	14		T13	65		T15	46
valid_sources[0x39]	288501	1			T1	4		T3	3		T12	12
valid_sources[0x3a]	362001	1			T1	1		T2	3		T12	28
valid_sources[0x3b]	286950	1			T1	1		T4	8		T12	28
valid_sources[0x3c]	416476	1			T1	2		T2	10		T12	12
valid_sources[0x3d]	286734	1			T1	4		T4	2		T13	36
valid_sources[0x3e]	287528	1			T1	1		T2	12		T3	3
valid_sources[0x3f]	463354	1			T1	3		T2	15		T12	2
valid_sources[0x40]	284488	1			T1	1		T2	8		T12	19
valid_sources[0x41]	287223	1			T4	1		T12	13		T13	11
valid_sources[0x42]	289472	1			T1	3		T2	2		T3	5
valid_sources[0x43]	286064	1			T1	3		T2	9		T3	10
valid_sources[0x44]	288781	1			T1	1		T2	7		T12	9
valid_sources[0x45]	285099	1			T2	3		T4	1		T12	11
valid_sources[0x46]	321479	1			T1	1		T12	7		T13	21
valid_sources[0x47]	289049	1			T1	2		T12	22		T13	43
valid_sources[0x48]	282388	1			T1	1		T2	6		T4	1
valid_sources[0x49]	423695	1			T12	22		T13	28		T15	53
valid_sources[0x4a]	332561	1			T1	5		T3	5		T12	9
valid_sources[0x4b]	459043	1			T1	1		T2	4		T4	3
valid_sources[0x4c]	284084	1			T1	6		T12	10		T13	18
valid_sources[0x4d]	393150	1			T1	1		T2	1		T19	1
valid_sources[0x4e]	288182	1			T4	6		T12	10		T13	35
valid_sources[0x4f]	285585	1			T1	2		T2	7		T12	9
valid_sources[0x50]	284910	1			T1	3		T2	2		T12	16
valid_sources[0x51]	296948	1			T4	1		T12	13		T13	59
valid_sources[0x52]	289784	1			T1	3		T2	8		T3	2
valid_sources[0x53]	288562	1			T2	6		T3	1		T12	11
valid_sources[0x54]	286013	1			T1	1		T3	2		T4	1
valid_sources[0x55]	293452	1			T1	4		T2	4		T13	43
valid_sources[0x56]	288445	1			T1	4		T2	1		T3	3
valid_sources[0x57]	284276	1			T1	8		T2	1		T3	4
valid_sources[0x58]	904467	1			T1	1		T3	1		T4	2
valid_sources[0x59]	288595	1			T1	2		T4	1		T12	10
valid_sources[0x5a]	284908	1			T1	2		T2	1		T19	3
valid_sources[0x5b]	286409	1			T2	8		T4	1		T12	6
valid_sources[0x5c]	287543	1			T1	2		T12	22		T13	4
valid_sources[0x5d]	286429	1			T1	2		T4	1		T12	20
valid_sources[0x5e]	290013	1			T1	2		T2	1		T4	6
valid_sources[0x5f]	285645	1			T1	5		T2	8		T3	2
valid_sources[0x60]	310801	1			T1	6		T4	2		T12	13
valid_sources[0x61]	287093	1			T1	7		T12	18		T13	12
valid_sources[0x62]	286372	1			T1	1		T2	1		T12	7
valid_sources[0x63]	286143	1			T2	2		T12	8		T13	12
valid_sources[0x64]	289021	1			T1	2		T2	7		T12	24
valid_sources[0x65]	292393	1			T3	1		T12	27		T13	40
valid_sources[0x66]	457324	1			T1	2		T3	6		T4	1
valid_sources[0x67]	286822	1			T1	2		T2	1		T4	1
valid_sources[0x68]	288784	1			T1	6		T12	17		T13	59
valid_sources[0x69]	285096	1			T1	1		T12	14		T13	103
valid_sources[0x6a]	1217227	1			T1	8		T12	10		T13	14
valid_sources[0x6b]	287494	1			T1	2		T2	1		T3	1
valid_sources[0x6c]	284845	1			T1	4		T2	4		T12	1
valid_sources[0x6d]	285684	1			T1	5		T3	5		T4	3
valid_sources[0x6e]	286499	1			T1	2		T2	3		T3	1
valid_sources[0x6f]	414971	1			T12	9		T13	21		T15	51
valid_sources[0x70]	289458	1			T1	3		T4	2		T12	21
valid_sources[0x71]	286259	1			T1	2		T2	2		T4	4
valid_sources[0x72]	350478	1			T1	7		T2	2		T12	29
valid_sources[0x73]	299114	1			T1	3		T12	6		T13	33
valid_sources[0x74]	430947	1			T1	2		T3	2		T12	12
valid_sources[0x75]	289180	1			T1	4		T2	2		T4	2
valid_sources[0x76]	1105543	1			T2	1		T12	20		T13	38
valid_sources[0x77]	289077	1			T1	2		T2	3		T12	25
valid_sources[0x78]	287477	1			T1	2		T3	3		T12	6
valid_sources[0x79]	290532	1			T1	1		T12	1		T13	47
valid_sources[0x7a]	286271	1			T1	4		T3	5		T4	1
valid_sources[0x7b]	286242	1			T1	7		T2	2		T4	2
valid_sources[0x7c]	289040	1			T1	1		T3	2		T4	1
valid_sources[0x7d]	287252	1			T3	3		T12	3		T13	46
valid_sources[0x7e]	290856	1			T1	1		T3	3		T4	1
valid_sources[0x7f]	286560	1			T1	10		T2	1		T3	4
valid_sources[0x80]	327572	1			T1	7		T2	8		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24013268

1

T1

215

T2

211

T3

74

values[0x0]

all_enables

biggest_size

13431627

1

T1

114

T2

114

T3

42

values[0x1]

all_enables

biggest_size

12155201

1

T1

102

T2

114

T3

46