Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

39986578

1

T1

205

T2

156

T3

37

full_word

49601295

1

T1

431

T2

439

T3

162

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	89587563	1			T1	636		T2	595		T3	199
auto[TlIntgErrCmd]	95	1			T60	4		T125	5		T126	5
auto[TlIntgErrData]	111	1			T60	5		T125	8		T126	3
auto[TlIntgErrBoth]	104	1			T60	1		T125	7		T126	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48604337

1

T1

329

T2

309

T3

83

auto[1]

40983536

1

T1

307

T2

286

T3

116

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24590599	1			T1	114		T2	98		T3	9
auto[TlIntgErrNone]	partial	auto[1]	15395691	1			T1	91		T2	58		T3	28
auto[TlIntgErrNone]	full_word	auto[0]	24013593	1			T1	215		T2	211		T3	74
auto[TlIntgErrNone]	full_word	auto[1]	25587680	1			T1	216		T2	228		T3	88
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T60	1		T125	1		T126	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T60	3		T125	2		T126	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T188	1		T189	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T125	2		T190	1		T191	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T60	1		T125	4		T126	2
auto[TlIntgErrData]	partial	auto[1]	55	1			T60	4		T125	4		T126	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T147	2		T191	1		T192	2
auto[TlIntgErrData]	full_word	auto[1]	2	1			T187	1		T193	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T60	1		T125	2		T126	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T125	4		T147	2		T190	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T125	1		T194	1		T195	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T196	1		T193	1		-	-