Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	546929325	3205	0	0
entropy_period_rd_A	546929325	1143	0	0
intr_enable_rd_A	546929325	1539	0	0
prefix_0_rd_A	546929325	1175	0	0
prefix_10_rd_A	546929325	1075	0	0
prefix_1_rd_A	546929325	960	0	0
prefix_2_rd_A	546929325	1013	0	0
prefix_3_rd_A	546929325	1041	0	0
prefix_4_rd_A	546929325	1098	0	0
prefix_5_rd_A	546929325	1134	0	0
prefix_6_rd_A	546929325	1149	0	0
prefix_7_rd_A	546929325	905	0	0
prefix_8_rd_A	546929325	1090	0	0
prefix_9_rd_A	546929325	988	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	3205	0	0
T59	2090	52	0	0
T61	3040	8	0	0
T124	16923	222	0	0
T125	10634	1	0	0
T129	7516	4	0	0
T130	2006	58	0	0
T133	4642	2	0	0
T134	4812	156	0	0
T135	2714	150	0	0
T146	3756	12	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	1143	0	0
T60	10511	37	0	0
T99	4352	22	0	0
T100	13254	52	0	0
T129	7516	4	0	0
T133	4642	5	0	0
T161	10095	48	0	0
T162	48418	424	0	0
T163	3194	5	0	0
T164	9584	48	0	0
T165	1963	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	1539	0	0
T60	10511	56	0	0
T99	4352	15	0	0
T100	13254	82	0	0
T124	16923	2	0	0
T129	7516	13	0	0
T133	4642	14	0	0
T161	10095	55	0	0
T162	48418	455	0	0
T163	3194	7	0	0
T166	1079	3	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	1175	0	0
T60	10511	37	0	0
T99	4352	10	0	0
T100	13254	57	0	0
T124	16923	9	0	0
T129	7516	18	0	0
T133	4642	6	0	0
T161	10095	10	0	0
T162	48418	498	0	0
T163	3194	8	0	0
T164	9584	30	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	1075	0	0
T60	10511	31	0	0
T99	4352	8	0	0
T100	13254	55	0	0
T129	7516	20	0	0
T133	4642	6	0	0
T161	10095	41	0	0
T162	48418	483	0	0
T163	3194	8	0	0
T164	9584	41	0	0
T165	1963	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	960	0	0
T60	10511	26	0	0
T99	4352	2	0	0
T100	13254	70	0	0
T129	7516	17	0	0
T133	4642	10	0	0
T161	10095	25	0	0
T162	48418	425	0	0
T163	3194	10	0	0
T164	9584	19	0	0
T165	1963	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	1013	0	0
T60	10511	19	0	0
T99	4352	17	0	0
T100	13254	70	0	0
T129	7516	13	0	0
T133	4642	9	0	0
T161	10095	19	0	0
T162	48418	442	0	0
T163	3194	5	0	0
T164	9584	56	0	0
T165	1963	1	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	1041	0	0
T60	10511	7	0	0
T99	4352	13	0	0
T100	13254	48	0	0
T124	16923	5	0	0
T129	7516	14	0	0
T133	4642	9	0	0
T161	10095	12	0	0
T162	48418	465	0	0
T163	3194	1	0	0
T164	9584	89	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	1098	0	0
T60	10511	28	0	0
T99	4352	9	0	0
T100	13254	54	0	0
T129	7516	25	0	0
T133	4642	8	0	0
T161	10095	24	0	0
T162	48418	471	0	0
T163	3194	5	0	0
T164	9584	49	0	0
T167	4229	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	1134	0	0
T60	10511	36	0	0
T99	4352	13	0	0
T100	13254	45	0	0
T129	7516	15	0	0
T133	4642	6	0	0
T161	10095	11	0	0
T162	48418	446	0	0
T163	3194	11	0	0
T164	9584	34	0	0
T165	1963	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	1149	0	0
T60	10511	25	0	0
T99	4352	21	0	0
T100	13254	51	0	0
T129	7516	21	0	0
T133	4642	7	0	0
T161	10095	29	0	0
T162	48418	472	0	0
T163	3194	11	0	0
T164	9584	31	0	0
T165	1963	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	905	0	0
T60	10511	32	0	0
T99	4352	15	0	0
T100	13254	43	0	0
T129	7516	13	0	0
T133	4642	2	0	0
T161	10095	19	0	0
T162	48418	450	0	0
T163	3194	2	0	0
T164	9584	14	0	0
T165	1963	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	1090	0	0
T60	10511	46	0	0
T99	4352	13	0	0
T100	13254	39	0	0
T129	7516	15	0	0
T133	4642	16	0	0
T161	10095	13	0	0
T162	48418	485	0	0
T163	3194	7	0	0
T164	9584	34	0	0
T165	1963	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546929325	988	0	0
T60	10511	54	0	0
T99	4352	9	0	0
T100	13254	50	0	0
T124	16923	7	0	0
T129	7516	16	0	0
T133	4642	9	0	0
T161	10095	8	0	0
T162	48418	450	0	0
T163	3194	5	0	0
T164	9584	38	0	0