Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43944689	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

52189936

1

T1

448

T2

443

T3

470

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51640772	1			T1	341		T2	303		T3	106
values[0x0]	21563714	1			T1	160		T2	141		T3	220
values[0x1]	22930139	1			T1	160		T2	141		T3	253

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34120144	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62014481

1

T1

501

T2

473

T3

506

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	304616	1			T1	1		T3	2		T13	9
valid_sources[0x01]	283488	1			T1	6		T3	1		T12	1
valid_sources[0x02]	287119	1			T1	6		T3	2		T13	12
valid_sources[0x03]	751212	1			T2	4		T3	6		T4	1
valid_sources[0x04]	347197	1			T3	4		T13	11		T14	16
valid_sources[0x05]	1454457	1			T3	1		T12	3		T13	10
valid_sources[0x06]	554432	1			T1	9		T2	6		T3	2
valid_sources[0x07]	288092	1			T1	5		T12	2		T13	6
valid_sources[0x08]	293071	1			T3	10		T12	5		T13	7
valid_sources[0x09]	309855	1			T1	1		T3	1		T13	6
valid_sources[0x0a]	286416	1			T3	5		T4	20		T13	5
valid_sources[0x0b]	285009	1			T1	5		T3	1		T13	9
valid_sources[0x0c]	283384	1			T1	10		T3	2		T13	8
valid_sources[0x0d]	294579	1			T1	2		T2	4		T3	5
valid_sources[0x0e]	303207	1			T1	6		T4	1		T12	1
valid_sources[0x0f]	806665	1			T1	2		T3	1		T12	1
valid_sources[0x10]	455812	1			T1	1		T3	1		T13	10
valid_sources[0x11]	349365	1			T1	1		T2	8		T3	1
valid_sources[0x12]	318006	1			T1	2		T2	9		T3	2
valid_sources[0x13]	279293	1			T2	6		T12	1		T13	16
valid_sources[0x14]	281381	1			T1	2		T3	1		T12	3
valid_sources[0x15]	284298	1			T2	3		T13	4		T14	19
valid_sources[0x16]	280435	1			T2	4		T3	3		T4	3
valid_sources[0x17]	282580	1			T1	4		T2	9		T3	3
valid_sources[0x18]	287769	1			T1	2		T3	4		T13	8
valid_sources[0x19]	395589	1			T1	2		T3	1		T4	3
valid_sources[0x1a]	285340	1			T1	3		T2	1		T3	2
valid_sources[0x1b]	280835	1			T1	3		T3	2		T13	8
valid_sources[0x1c]	282694	1			T1	1		T3	3		T13	9
valid_sources[0x1d]	456947	1			T1	3		T2	13		T3	5
valid_sources[0x1e]	282681	1			T1	5		T3	2		T12	3
valid_sources[0x1f]	283329	1			T1	1		T3	2		T12	4
valid_sources[0x20]	277476	1			T1	3		T2	10		T3	1
valid_sources[0x21]	279508	1			T3	1		T13	12		T14	11
valid_sources[0x22]	285650	1			T1	1		T3	1		T13	9
valid_sources[0x23]	282396	1			T12	3		T13	19		T14	18
valid_sources[0x24]	446671	1			T1	8		T3	10		T4	1
valid_sources[0x25]	285436	1			T1	2		T2	3		T3	1
valid_sources[0x26]	281952	1			T1	6		T3	6		T13	6
valid_sources[0x27]	284092	1			T2	2		T12	5		T13	13
valid_sources[0x28]	403150	1			T3	2		T12	6		T13	12
valid_sources[0x29]	1161834	1			T1	3		T2	14		T12	4
valid_sources[0x2a]	282779	1			T1	4		T3	8		T13	7
valid_sources[0x2b]	321540	1			T1	2		T3	1		T13	38098
valid_sources[0x2c]	287254	1			T1	4		T2	20		T3	2
valid_sources[0x2d]	283782	1			T1	2		T2	14		T3	4
valid_sources[0x2e]	282311	1			T1	4		T2	13		T3	2
valid_sources[0x2f]	291041	1			T13	10		T14	16		T15	4
valid_sources[0x30]	281101	1			T1	7		T2	4		T3	3
valid_sources[0x31]	283393	1			T3	3		T4	1		T12	2
valid_sources[0x32]	286931	1			T1	2		T2	3		T3	2
valid_sources[0x33]	284117	1			T1	1		T2	14		T13	8
valid_sources[0x34]	288062	1			T1	3		T3	6		T4	1
valid_sources[0x35]	284894	1			T3	4		T12	1		T13	15
valid_sources[0x36]	285874	1			T1	1		T3	1		T13	14
valid_sources[0x37]	286363	1			T1	2		T2	17		T13	10
valid_sources[0x38]	283156	1			T1	5		T2	9		T13	8
valid_sources[0x39]	318699	1			T1	5		T2	4		T3	6
valid_sources[0x3a]	282924	1			T1	1		T2	6		T3	3
valid_sources[0x3b]	282825	1			T1	11		T2	3		T3	3
valid_sources[0x3c]	301147	1			T1	3		T2	9		T12	8
valid_sources[0x3d]	285489	1			T1	2		T2	13		T3	3
valid_sources[0x3e]	460957	1			T1	4		T3	1		T12	5
valid_sources[0x3f]	278927	1			T1	1		T3	4		T4	4
valid_sources[0x40]	286905	1			T1	2		T3	6		T18	2
valid_sources[0x41]	282362	1			T1	5		T3	3		T13	8
valid_sources[0x42]	282730	1			T1	6		T3	1		T13	16
valid_sources[0x43]	280710	1			T1	1		T2	1		T3	1
valid_sources[0x44]	1105616	1			T1	5		T2	9		T3	1
valid_sources[0x45]	315338	1			T1	2		T3	3		T12	2
valid_sources[0x46]	342059	1			T1	3		T3	8		T13	12
valid_sources[0x47]	284622	1			T1	1		T12	14		T13	10
valid_sources[0x48]	281970	1			T12	2		T13	7		T14	11
valid_sources[0x49]	288985	1			T1	1		T3	3		T12	3
valid_sources[0x4a]	323772	1			T1	2		T3	1		T4	2
valid_sources[0x4b]	287323	1			T12	3		T13	4		T14	12
valid_sources[0x4c]	286274	1			T2	3		T4	1		T13	2
valid_sources[0x4d]	282082	1			T1	5		T13	8		T14	16
valid_sources[0x4e]	288174	1			T1	1		T3	2		T12	3
valid_sources[0x4f]	282690	1			T1	4		T3	4		T12	3
valid_sources[0x50]	284156	1			T1	2		T18	5		T12	1
valid_sources[0x51]	283843	1			T1	4		T3	5		T13	17
valid_sources[0x52]	283411	1			T12	25		T13	9		T14	10
valid_sources[0x53]	279555	1			T2	17		T3	2		T13	8
valid_sources[0x54]	343986	1			T1	3		T2	10		T3	2
valid_sources[0x55]	406856	1			T1	1		T2	1		T3	1
valid_sources[0x56]	438081	1			T1	4		T2	6		T3	3
valid_sources[0x57]	286770	1			T1	3		T3	4		T4	1
valid_sources[0x58]	285355	1			T1	1		T3	1		T13	5
valid_sources[0x59]	801058	1			T1	3		T2	5		T3	5
valid_sources[0x5a]	936026	1			T1	3		T2	4		T3	2
valid_sources[0x5b]	284491	1			T1	1		T12	2		T13	9
valid_sources[0x5c]	284648	1			T1	4		T3	3		T4	1
valid_sources[0x5d]	301948	1			T1	2		T3	3		T13	8
valid_sources[0x5e]	435877	1			T1	4		T3	3		T13	6
valid_sources[0x5f]	284874	1			T3	6		T4	2		T13	7
valid_sources[0x60]	286684	1			T3	6		T13	6		T14	12
valid_sources[0x61]	539700	1			T1	3		T3	5		T13	7
valid_sources[0x62]	290209	1			T3	3		T13	15		T14	12
valid_sources[0x63]	407493	1			T3	6		T12	1		T13	11
valid_sources[0x64]	416444	1			T2	11		T3	4		T12	1
valid_sources[0x65]	386194	1			T1	3		T3	2		T13	12
valid_sources[0x66]	285393	1			T1	1		T3	3		T4	7
valid_sources[0x67]	282678	1			T1	1		T12	1		T13	10
valid_sources[0x68]	445531	1			T1	2		T2	11		T3	5
valid_sources[0x69]	282849	1			T1	1		T2	24		T4	2
valid_sources[0x6a]	412718	1			T1	2		T2	3		T12	9
valid_sources[0x6b]	398441	1			T1	7		T3	8		T12	4
valid_sources[0x6c]	335284	1			T1	3		T12	7		T13	13
valid_sources[0x6d]	283628	1			T3	4		T12	11		T13	14
valid_sources[0x6e]	298657	1			T4	3		T13	6		T14	13
valid_sources[0x6f]	282681	1			T1	2		T4	3		T13	10
valid_sources[0x70]	286532	1			T1	1		T13	7		T14	9
valid_sources[0x71]	343231	1			T1	3		T2	7		T3	6
valid_sources[0x72]	281999	1			T1	3		T3	3		T4	5
valid_sources[0x73]	286958	1			T1	4		T3	1		T12	7
valid_sources[0x74]	284846	1			T1	2		T13	5		T14	17
valid_sources[0x75]	282890	1			T1	6		T3	1		T13	6
valid_sources[0x76]	290532	1			T3	6		T13	7		T14	12
valid_sources[0x77]	284260	1			T1	1		T3	2		T4	1
valid_sources[0x78]	285043	1			T1	5		T2	13		T3	6
valid_sources[0x79]	282496	1			T1	4		T3	2		T12	5
valid_sources[0x7a]	409149	1			T2	5		T13	10		T14	12
valid_sources[0x7b]	280705	1			T4	3		T13	4		T14	14
valid_sources[0x7c]	283588	1			T1	5		T3	1		T13	5
valid_sources[0x7d]	282743	1			T3	1		T4	3		T12	1
valid_sources[0x7e]	880739	1			T1	3		T3	3		T13	5
valid_sources[0x7f]	283295	1			T3	5		T13	13		T14	11
valid_sources[0x80]	934759	1			T1	4		T3	1		T13	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24548989

1

T1

231

T2

215

T3

23

values[0x0]

all_enables

biggest_size

14529353

1

T1

120

T2

118

T3

212

values[0x1]

all_enables

biggest_size

13111594

1

T1

97

T2

110

T3

235