Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43972397

1

T1

213

T2

142

T3

109

full_word

52191528

1

T1

448

T2

443

T3

470

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	96163655	1			T1	661		T2	585		T3	579
auto[TlIntgErrCmd]	95	1			T58	5		T114	2		T115	4
auto[TlIntgErrData]	89	1			T58	2		T114	4		T115	5
auto[TlIntgErrBoth]	86	1			T58	3		T114	4		T115	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51646776

1

T1

341

T2

303

T3

106

auto[1]

44517149

1

T1

320

T2

282

T3

473

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	27097258	1			T1	110		T2	88		T3	83
auto[TlIntgErrNone]	partial	auto[1]	16874896	1			T1	103		T2	54		T3	26
auto[TlIntgErrNone]	full_word	auto[0]	24549411	1			T1	231		T2	215		T3	23
auto[TlIntgErrNone]	full_word	auto[1]	27642090	1			T1	217		T2	228		T3	447
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T58	1		T115	1		T135	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T58	4		T115	2		T135	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T114	2		T181	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T115	1		T182	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T58	2		T114	1		T115	4
auto[TlIntgErrData]	partial	auto[1]	41	1			T114	2		T115	1		T135	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T136	1		T183	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T114	1		T136	1		T182	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1			T58	1		T114	2		T115	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T58	1		T114	2		T135	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T184	2		T185	1		T180	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T58	1		T179	1		T185	1