Unified Coverage Report :: Module :: sha3

Module : sha3

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.32	97.56	88.89		81.82	93.33	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3	95.96	97.56	88.89		100.00	93.33	100.00

---

Module Instance : tb.dut.u_sha3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	97.56	88.89		100.00	93.33	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.62	91.91	88.51	100.00	83.33	92.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak	81.47	81.77	88.24	100.00	40.00	78.79	100.00
u_pad	97.26	99.42	88.37	100.00	100.00	95.79	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3

	Line No.	Total	Covered	Percent
TOTAL		82	80	97.56
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	184	5	5	100.00
ALWAYS	198	3	3	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	207	6	6	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
ALWAYS	227	3	3	100.00
ALWAYS	237	38	38	100.00
ALWAYS	332	3	3	100.00
ALWAYS	349	12	10	83.33

137                       logic round_count_error, msg_count_error;
138        1/1            assign count_error_o =  round_count_error | msg_count_error;
           Tests:       T1 T2 T3 
139                     
140                       logic sha3_state_error;
141                       logic keccak_round_state_error;
142                       logic sha3pad_state_error;
143                     
144        1/1            assign sparse_fsm_error_o = sha3_state_error | keccak_round_state_error | sha3pad_state_error;
           Tests:       T1 T2 T3 
145                     
146                       // Keccak rst_storage is asserted unexpectedly
147                       logic keccak_storage_rst_error;
148        1/1            assign keccak_storage_rst_error_o = keccak_storage_rst_error;
           Tests:       T1 T2 T3 
149                     
150                       /////////////////
151                       // Connections //
152                       /////////////////
153                     
154                       logic                       keccak_valid;
155                       logic [KeccakMsgAddrW-1:0]  keccak_addr;
156                       logic [MsgWidth-1:0]        keccak_data [Share];
157                       logic                       keccak_ready;
158                     
159                       // Keccak round run signal can be controlled by sha3pad and also by software
160                       // after all message feeding is done. it is mainly used for sponge squeezing
161                       // operation after absorbing is completed when output length is longer than
162                       // the block size.
163                       logic keccak_run, sha3pad_keccak_run, sw_keccak_run;
164                       logic keccak_run_req_d, keccak_run_req_q;
165                       logic keccak_triggered_d, keccak_triggered_q;
166                       logic keccak_complete;
167                     
168                       // Announce that we want to run the Keccak core and tell other blocks to go
169                       // quiet. Keep holding the REQ until the Keccak core is done with the
170                       // processing. The keccak_complete signal is received once the Keccak core
171                       // is back in the Idle state and again susceptible to keccak_run.
172        1/1            assign run_req_o = keccak_run_req_d;
           Tests:       T1 T2 T3 
173        1/1            assign keccak_run_req_d =
           Tests:       T1 T2 T3 
174                           sha3pad_keccak_run || sw_keccak_run ? 1'b 1 :
175                           keccak_complete                     ? 1'b 0 : keccak_run_req_q;
176                     
177                       // Trigger the Keccak engine with a single pulse upon receiving the ACK.
178        1/1            assign keccak_run = run_req_o & run_ack_i & ~keccak_triggered_q;
           Tests:       T1 T2 T3 
179        1/1            assign keccak_triggered_d =
           Tests:       T1 T2 T3 
180                           keccak_run      ? 1'b 1 :
181                           keccak_complete ? 1'b 0 : keccak_triggered_q;
182                     
183                       always_ff @(posedge clk_i or negedge rst_ni) begin
184        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
185        1/1                keccak_run_req_q <= 1'b 0;
           Tests:       T1 T2 T3 
186        1/1                keccak_triggered_q <= 1'b 0;
           Tests:       T1 T2 T3 
187                         end else begin
188        1/1                keccak_run_req_q <= keccak_run_req_d;
           Tests:       T1 T2 T3 
189        1/1                keccak_triggered_q <= keccak_triggered_d;
           Tests:       T1 T2 T3 
190                         end
191                       end
192                     
193                       // Absorb pulse output : used to generate interrupts
194                       // Latch absorbed signal as kmac_keymgr asserts `CmdDone` when it sees
195                       // `absorbed` signal. When this signal goes out, the state is still in
196                       // `StAbsorb`. Next state is `StSqueeze`.
197                       always_ff @(posedge clk_i or negedge rst_ni) begin
198        2/2              if (!rst_ni) absorbed_o <= prim_mubi_pkg::MuBi4False;
           Tests:       T1 T2 T3  | T1 T2 T3 
199        1/1              else         absorbed_o <= absorbed;
           Tests:       T1 T2 T3 
200                       end
201                     
202                       // Squeezing output
203        1/1            assign squeezing_o = squeezing;
           Tests:       T1 T2 T3 
204                     
205                       // processing
206                       always_ff @(posedge clk_i or negedge rst_ni) begin
207        2/2              if (!rst_ni)        processing <= 1'b 0;
           Tests:       T1 T2 T3  | T1 T2 T3 
208        2/2              else if (process_i) processing <= 1'b 1;
           Tests:       T1 T2 T3  | T1 T2 T3 
209        1/1              else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
           Tests:       T1 T2 T3 
210        1/1                processing <= 1'b 0;
           Tests:       T1 T2 T3 
211                         end
                        MISSING_ELSE
212                       end
213                     
214        1/1            assign block_processed_o = keccak_complete;
           Tests:       T1 T2 T3 
215                     
216                       // State connection
217        1/1            assign state_valid_o = state_valid;
           Tests:       T1 T2 T3 
218        1/1            assign state_o = state_guarded;
           Tests:       T1 T2 T3 
219                     
220        1/1            assign sha3_fsm_o = sparse2logic(st);
           Tests:       T1 T2 T3 
221                     
222                       ///////////////////
223                       // State Machine //
224                       ///////////////////
225                     
226                       // State Register
227        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse):
227.1                   `ifdef SIMULATION                                   
227.2                       prim_sparse_fsm_flop #(                           
227.3                         .StateEnumT(sha3_st_sparse_e),                            
227.4                         .Width($bits(sha3_st_sparse_e)),                          
227.5                         .ResetValue($bits(sha3_st_sparse_e)'(StIdle_sparse)),          
227.6                         .EnableAlertTriggerSVA(1), 
227.7                         .CustomForceName("st")          
227.8                       ) u_state_regs (                                        
227.9                         .clk_i   ( clk_i   ),                           
227.10                        .rst_ni  ( rst_ni ),                           
227.11                        .state_i ( st_d     ),                           
227.12                        .state_o (         )                            
227.13                      );                                                
227.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
227.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
227.16     1/1                st <= StIdle_sparse;                                
           Tests:       T1 T2 T3 
227.17                      end else begin                                    
227.18     1/1                st <= st_d;                                     
           Tests:       T1 T2 T3 
227.19                      end                                               
227.20                    end  
227.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (st === u_state_regs.state_o))       
227.22                      else begin                                                                           
227.23                        `ifdef UVM                                                                               
227.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
227.25                                              "../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv", 227, "", 1);                                
227.26                  `else                                                                                    
227.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
227.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
227.29                  `endif                                                              
227.30                      end 
227.31                    `else                                               
227.32                      prim_sparse_fsm_flop #(                           
227.33                        .StateEnumT(sha3_st_sparse_e),                            
227.34                        .Width($bits(sha3_st_sparse_e)),                          
227.35                        .ResetValue($bits(sha3_st_sparse_e)'(StIdle_sparse)),          
227.36                        .EnableAlertTriggerSVA(1)  
227.37                      ) u_state_regs (                                        
227.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
227.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
227.40                        .state_i ( st_d     ),                           
227.41                        .state_o ( st     )                            
227.42                      );                                                
227.43                    `endif228                     
229                     
230                       // Next State and Output Logic
231                       // Mainly the FSM controls the input signal access
232                       // StIdle:    only start_i signal is allowed
233                       // StAbsorb:  only process_i signal is allowed
234                       // StSqueeze: only run_i, done_i signal is allowed
235                     
236                       always_comb begin
237        1/1              st_d = st;
           Tests:       T1 T2 T3 
238                     
239                         // default output values
240        1/1              keccak_start = 1'b 0;
           Tests:       T1 T2 T3 
241        1/1              keccak_process = 1'b 0;
           Tests:       T1 T2 T3 
242        1/1              sw_keccak_run = 1'b 0;
           Tests:       T1 T2 T3 
243        1/1              keccak_done = prim_mubi_pkg::MuBi4False;
           Tests:       T1 T2 T3 
244                     
245        1/1              squeezing = 1'b 0;
           Tests:       T1 T2 T3 
246                     
247        1/1              state_valid = 1'b 0;
           Tests:       T1 T2 T3 
248        1/1              mux_sel = MuxGuard ;
           Tests:       T1 T2 T3 
249                     
250        1/1              sha3_state_error = 1'b 0;
           Tests:       T1 T2 T3 
251                     
252        1/1              unique case (st)
           Tests:       T1 T2 T3 
253                           StIdle_sparse: begin
254        1/1                  if (start_i) begin
           Tests:       T1 T2 T3 
255        1/1                    st_d = StAbsorb_sparse;
           Tests:       T1 T2 T3 
256                     
257        1/1                    keccak_start = 1'b 1;
           Tests:       T1 T2 T3 
258                             end else begin
259        1/1                    st_d = StIdle_sparse;
           Tests:       T1 T2 T3 
260                             end
261                           end
262                     
263                           StAbsorb_sparse: begin
264        1/1                  if (process_i && !processing) begin
           Tests:       T1 T2 T3 
265        1/1                    st_d = StAbsorb_sparse;
           Tests:       T1 T2 T3 
266                     
267        1/1                    keccak_process = 1'b 1;
           Tests:       T1 T2 T3 
268        1/1                  end else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
           Tests:       T1 T2 T3 
269        1/1                    st_d = StSqueeze_sparse;
           Tests:       T1 T2 T3 
270                             end else begin
271        1/1                    st_d = StAbsorb_sparse;
           Tests:       T1 T2 T3 
272                             end
273                           end
274                     
275                           StSqueeze_sparse: begin
276        1/1                  state_valid = 1'b 1;
           Tests:       T1 T2 T3 
277        1/1                  mux_sel = MuxRelease; // Expose state to register interface
           Tests:       T1 T2 T3 
278                     
279        1/1                  squeezing = 1'b 1;
           Tests:       T1 T2 T3 
280                     
281        1/1                  if (run_i) begin
           Tests:       T1 T2 T3 
282        1/1                    st_d = StManualRun_sparse;
           Tests:       T13 T14 T5 
283                     
284        1/1                    sw_keccak_run = 1'b 1;
           Tests:       T13 T14 T5 
285        1/1                  end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
           Tests:       T1 T2 T3 
286        1/1                    st_d = StFlush_sparse;
           Tests:       T1 T2 T3 
287                     
288        1/1                    keccak_done = done_i;
           Tests:       T1 T2 T3 
289                             end else begin
290        1/1                    st_d = StSqueeze_sparse;
           Tests:       T1 T2 T12 
291                             end
292                           end
293                     
294                           StManualRun_sparse: begin
295        1/1                  if (keccak_complete) begin
           Tests:       T13 T14 T5 
296        1/1                    st_d = StSqueeze_sparse;
           Tests:       T13 T14 T5 
297                             end else begin
298        1/1                    st_d = StManualRun_sparse;
           Tests:       T13 T14 T5 
299                             end
300                           end
301                     
302                           StFlush_sparse: begin
303        1/1                  st_d = StIdle_sparse;
           Tests:       T1 T2 T3 
304                           end
305                     
306                           StTerminalError_sparse: begin
307                             //this state is terminal
308        1/1                  st_d = StTerminalError_sparse;
           Tests:       T4 T5 T6 
309        1/1                  sha3_state_error = 1'b 1;
           Tests:       T4 T5 T6 
310                           end
311                     
312                           default: begin
313                             st_d = StTerminalError_sparse;
314                             sha3_state_error = 1'b 1;
315                           end
316                         endcase
317                     
318                         // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC
319                         // Unconditionally jump into the terminal error state
320                         // if the life cycle controller triggers an escalation.
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                st_d = StTerminalError_sparse;
           Tests:       T4 T5 T6 
323                         end
                        MISSING_ELSE
324                       end
325                     
326                       //////////////
327                       // Datapath //
328                       //////////////
329                     
330                       // State --> Digest output
331                       always_comb begin : state_guarded_mux
332        1/1              unique case (mux_sel)
           Tests:       T1 T2 T3 
333        1/1                MuxGuard:   state_guarded = '{default: '0};
           Tests:       T1 T2 T3 
334        1/1                MuxRelease: state_guarded = state;
           Tests:       T1 T2 T3 
335                           default:    state_guarded = '{default: '0}; // a valid, safe output
336                         endcase
337                       end
338                     
339                     
340                       // Error Detecting
341                       // ErrSha3SwControl:
342                       //   info[ 0]: start_i set
343                       //   info[ 1]: process_i set
344                       //   info[ 2]: run_i set
345                       //   info[ 3]: done_i set
346                       //  - Sw set process_i, run_i, done_i without start_i
347                     
348                       always_comb begin
349        1/1              error_o = '{valid: 1'b0, code: ErrNone, info: '0};
           Tests:       T1 T2 T3 
350                     
351        1/1              unique case (st)
           Tests:       T1 T2 T3 
352                           StIdle_sparse: begin
353        1/1                  if (process_i || run_i ||
           Tests:       T1 T2 T3 
354                               prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
355        1/1                    error_o = '{
           Tests:       T14 T27 T34 
356                                 valid: 1'b 1,
357                                 code: ErrSha3SwControl,
358                                 info: 24'({done_i, run_i, process_i, start_i})
359                               };
360                             end
                        MISSING_ELSE
361                           end
362                     
363                           StAbsorb_sparse: begin
364        1/1                  if (start_i || run_i || prim_mubi_pkg::mubi4_test_true_loose(done_i)
           Tests:       T1 T2 T3 
365                               || (process_i && processing)) begin
366        1/1                    error_o = '{
           Tests:       T14 T27 T34 
367                                 valid: 1'b 1,
368                                 code: ErrSha3SwControl,
369                                 info: 24'({done_i, run_i, process_i, start_i})
370                               };
371                             end
                        MISSING_ELSE
372                           end
373                     
374                           StSqueeze_sparse: begin
375        1/1                  if (start_i || process_i) begin
           Tests:       T1 T2 T3 
376        0/1     ==>            error_o = '{
377                                 valid: 1'b 1,
378                                 code: ErrSha3SwControl,
379                                 info: 24'({done_i, run_i, process_i, start_i})
380                               };
381                             end
                        MISSING_ELSE
382                           end
383                     
384                           StManualRun_sparse: begin
385        1/1                  if (start_i || process_i || run_i ||
           Tests:       T13 T14 T5 
386                               prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
387        1/1                    error_o = '{
           Tests:       T14 T27 T34 
388                                 valid: 1'b 1,
389                                 code: ErrSha3SwControl,
390                                 info: 24'({done_i, run_i, process_i, start_i})
391                               };
392                             end
                        MISSING_ELSE
393                           end
394                     
395                           StFlush_sparse: begin
396        1/1                  if (start_i || process_i || run_i ||
           Tests:       T1 T2 T3 
397                               prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
398        0/1     ==>            error_o = '{
399                                 valid: 1'b 1,
400                                 code: ErrSha3SwControl,
401                                 info: 24'({done_i, run_i, process_i, start_i})
402                               };
403                             end
                        MISSING_ELSE

---

Cond Coverage for Module : sha3

	Total	Covered	Percent
Conditions	27	24	88.89
Logical	27	24	88.89
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       144
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T9,T10,T11
0	1	0	Covered	T9,T10,T11
1	0	0	Covered	T9,T10,T11

 LINE       173
 EXPRESSION ((sha3pad_keccak_run || sw_keccak_run) ? 1'b1 : (keccak_complete ? 1'b0 : keccak_run_req_q))
             ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       173
 SUB-EXPRESSION (sha3pad_keccak_run || sw_keccak_run)
                 ---------1--------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T5
1	0	Covered	T1,T2,T3

 LINE       173
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_run_req_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (run_req_o & run_ack_i & ((~keccak_triggered_q)))
             ----1----   ----2----   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       179
 EXPRESSION (keccak_run ? 1'b1 : (keccak_complete ? 1'b0 : keccak_triggered_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       179
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_triggered_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       264
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Module : sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	11	9	81.82
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	255	Covered	T1,T2,T3
StFlush_sparse	286	Covered	T1,T2,T3
StIdle_sparse	259	Covered	T1,T2,T3
StManualRun_sparse	282	Covered	T13,T14,T5
StSqueeze_sparse	269	Covered	T1,T2,T3
StTerminalError_sparse	308	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
StAbsorb_sparse->StSqueeze_sparse	269	Covered	T1,T2,T3
StAbsorb_sparse->StTerminalError_sparse	322	Covered	T4,T6,T39
StFlush_sparse->StIdle_sparse	303	Covered	T1,T2,T3
StFlush_sparse->StTerminalError_sparse	322	Not Covered
StIdle_sparse->StAbsorb_sparse	255	Covered	T1,T2,T3
StIdle_sparse->StTerminalError_sparse	322	Covered	T5,T9,T10
StManualRun_sparse->StSqueeze_sparse	296	Covered	T13,T14,T5
StManualRun_sparse->StTerminalError_sparse	322	Not Covered
StSqueeze_sparse->StFlush_sparse	286	Covered	T1,T2,T3
StSqueeze_sparse->StManualRun_sparse	282	Covered	T13,T14,T5
StSqueeze_sparse->StTerminalError_sparse	322	Covered	T59,T60,T61

---

Branch Coverage for Module : sha3

	Line No.	Total	Covered	Percent
Branches		45	42	93.33
TERNARY	173	3	3	100.00
TERNARY	179	3	3	100.00
IF	184	2	2	100.00
IF	198	2	2	100.00
IF	207	4	4	100.00
IF	227	2	2	100.00
CASE	252	13	13	100.00
IF	321	2	2	100.00
CASE	332	3	2	66.67
CASE	351	11	9	81.82

173          assign keccak_run_req_d =
                                      
174              sha3pad_keccak_run || sw_keccak_run ? 1'b 1 :
                                                     -1-  
                                                     ==>  
175              keccak_complete                     ? 1'b 0 : keccak_run_req_q;
                                                     -2-  
                                                     ==>  
                                                     ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

179          assign keccak_triggered_d =
                                        
180              keccak_run      ? 1'b 1 :
                                 -1-  
                                 ==>  
181              keccak_complete ? 1'b 0 : keccak_triggered_q;
                                 -2-  
                                 ==>  
                                 ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

184            if (!rst_ni) begin
               -1-  
185              keccak_run_req_q <= 1'b 0;
                 ==>
186              keccak_triggered_q <= 1'b 0;
187            end else begin
188              keccak_run_req_q <= keccak_run_req_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

198            if (!rst_ni) absorbed_o <= prim_mubi_pkg::MuBi4False;
               -1-  
               ==>
199            else         absorbed_o <= absorbed;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

207            if (!rst_ni)        processing <= 1'b 0;
               -1-  
               ==>
208            else if (process_i) processing <= 1'b 1;
                    -2-  
               ==>
209            else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
                    -3-  
210              processing <= 1'b 0;
                 ==>
211            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

227          `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse)
             -1-                                                                              
             ==>                                                                              
             ==>                                                                              

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

252            unique case (st)
                      -1-  
253              StIdle_sparse: begin
254                if (start_i) begin
                   -2-  
255                  st_d = StAbsorb_sparse;
                     ==>
256        
257                  keccak_start = 1'b 1;
258                end else begin
259                  st_d = StIdle_sparse;
                     ==>
260                end
261              end
262        
263              StAbsorb_sparse: begin
264                if (process_i && !processing) begin
                   -3-  
265                  st_d = StAbsorb_sparse;
                     ==>
266        
267                  keccak_process = 1'b 1;
268                end else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
                            -4-  
269                  st_d = StSqueeze_sparse;
                     ==>
270                end else begin
271                  st_d = StAbsorb_sparse;
                     ==>
272                end
273              end
274        
275              StSqueeze_sparse: begin
276                state_valid = 1'b 1;
277                mux_sel = MuxRelease; // Expose state to register interface
278        
279                squeezing = 1'b 1;
280        
281                if (run_i) begin
                   -5-  
282                  st_d = StManualRun_sparse;
                     ==>
283        
284                  sw_keccak_run = 1'b 1;
285                end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
                            -6-  
286                  st_d = StFlush_sparse;
                     ==>
287        
288                  keccak_done = done_i;
289                end else begin
290                  st_d = StSqueeze_sparse;
                     ==>
291                end
292              end
293        
294              StManualRun_sparse: begin
295                if (keccak_complete) begin
                   -7-  
296                  st_d = StSqueeze_sparse;
                     ==>
297                end else begin
298                  st_d = StManualRun_sparse;
                     ==>
299                end
300              end
301        
302              StFlush_sparse: begin
303                st_d = StIdle_sparse;
                   ==>
304              end
305        
306              StTerminalError_sparse: begin
307                //this state is terminal
308                st_d = StTerminalError_sparse;
                   ==>
309                sha3_state_error = 1'b 1;
310              end
311        
312              default: begin
313                st_d = StTerminalError_sparse;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle_sparse	0	-	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	1	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	1	-	-	Covered	T13,T14,T5
StSqueeze_sparse	-	-	-	0	1	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	0	0	-	Covered	T1,T2,T12
StManualRun_sparse	-	-	-	-	-	1	Covered	T13,T14,T5
StManualRun_sparse	-	-	-	-	-	0	Covered	T13,T14,T5
StFlush_sparse	-	-	-	-	-	-	Covered	T1,T2,T3
StTerminalError_sparse	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	Covered	T9,T10,T11

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
               -1-  
322              st_d = StTerminalError_sparse;
                 ==>
323            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

332            unique case (mux_sel)
                      -1-  
333              MuxGuard:   state_guarded = '{default: '0};
                 ==>
334              MuxRelease: state_guarded = state;
                 ==>
335              default:    state_guarded = '{default: '0}; // a valid, safe output
                 ==>

Branches:

-1-	Status	Tests
MuxGuard	Covered	T1,T2,T3
MuxRelease	Covered	T1,T2,T3
default	Not Covered

351            unique case (st)
                      -1-  
352              StIdle_sparse: begin
353                if (process_i || run_i ||
                   -2-  
354                  prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
355                  error_o = '{
                     ==>
356                    valid: 1'b 1,
357                    code: ErrSha3SwControl,
358                    info: 24'({done_i, run_i, process_i, start_i})
359                  };
360                end
                   MISSING_ELSE
                   ==>
361              end
362        
363              StAbsorb_sparse: begin
364                if (start_i || run_i || prim_mubi_pkg::mubi4_test_true_loose(done_i)
                   -3-  
365                  || (process_i && processing)) begin
366                  error_o = '{
                     ==>
367                    valid: 1'b 1,
368                    code: ErrSha3SwControl,
369                    info: 24'({done_i, run_i, process_i, start_i})
370                  };
371                end
                   MISSING_ELSE
                   ==>
372              end
373        
374              StSqueeze_sparse: begin
375                if (start_i || process_i) begin
                   -4-  
376                  error_o = '{
                     ==>
377                    valid: 1'b 1,
378                    code: ErrSha3SwControl,
379                    info: 24'({done_i, run_i, process_i, start_i})
380                  };
381                end
                   MISSING_ELSE
                   ==>
382              end
383        
384              StManualRun_sparse: begin
385                if (start_i || process_i || run_i ||
                   -5-  
386                  prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
387                  error_o = '{
                     ==>
388                    valid: 1'b 1,
389                    code: ErrSha3SwControl,
390                    info: 24'({done_i, run_i, process_i, start_i})
391                  };
392                end
                   MISSING_ELSE
                   ==>
393              end
394        
395              StFlush_sparse: begin
396                if (start_i || process_i || run_i ||
                   -6-  
397                  prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
398                  error_o = '{
                     ==>
399                    valid: 1'b 1,
400                    code: ErrSha3SwControl,
401                    info: 24'({done_i, run_i, process_i, start_i})
402                  };
403                end
                   MISSING_ELSE
                   ==>
404              end
405        
406              default: begin
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Covered	T14,T27,T34
StIdle_sparse	0	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	Covered	T14,T27,T34
StAbsorb_sparse	-	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Covered	T1,T2,T3
StManualRun_sparse	-	-	-	1	-	Covered	T14,T27,T34
StManualRun_sparse	-	-	-	0	-	Covered	T13,T5,T48
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Covered	T4,T5,T6

---

Assert Coverage for Module : sha3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrDetection_A	567132835	8158494	0	0
FsmKnown_A	567019212	566898845	0	0
KeccakIdleWhenNoRunHs_A	567132835	21000616	0	0
MuxSelKnown_A	567132835	567007961	0	0
SwRunInSqueezing_a	567132835	120486	0	0
gen_chk_digest_unmasked.StateZeroInvalid_A	567132835	482341611	0	0
u_state_regs_A	567132835	567007961	0	0

ErrDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	8158494	0	0
T5	13685	0	0	0
T14	132067	82202	0	0
T15	6666	0	0	0
T16	2469	0	0	0
T17	11295	0	0	0
T19	1321	0	0	0
T20	87123	0	0	0
T21	36222	0	0	0
T27	0	69290	0	0
T34	0	116395	0	0
T35	86217	0	0	0
T80	26205	0	0	0
T84	0	159840	0	0
T85	0	459719	0	0
T86	0	115341	0	0
T87	0	71172	0	0
T88	0	268992	0	0
T89	0	261818	0	0
T90	0	23492	0	0

FsmKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567019212	566898845	0	0
T1	2517	2441	0	0
T2	2527	2429	0	0
T3	42818	42730	0	0
T4	2559	2405	0	0
T12	3035	2954	0	0
T13	665515	665440	0	0
T14	132067	131972	0	0
T15	6666	6605	0	0
T18	1132	1045	0	0
T19	1321	1236	0	0

KeccakIdleWhenNoRunHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	21000616	0	0
T1	2517	240	0	0
T2	2527	240	0	0
T3	42818	648	0	0
T4	2559	49	0	0
T12	3035	240	0	0
T13	665515	10944	0	0
T14	132067	11616	0	0
T15	6666	240	0	0
T16	0	240	0	0
T17	0	264	0	0
T18	1132	0	0	0
T19	1321	0	0	0

MuxSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	567007961	0	0
T1	2517	2441	0	0
T2	2527	2429	0	0
T3	42818	42730	0	0
T4	2559	2405	0	0
T12	3035	2954	0	0
T13	665515	665440	0	0
T14	132067	131972	0	0
T15	6666	6605	0	0
T18	1132	1045	0	0
T19	1321	1236	0	0

SwRunInSqueezing_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	120486	0	0
T5	13685	4	0	0
T13	665515	117	0	0
T14	132067	161	0	0
T15	6666	0	0	0
T16	2469	0	0	0
T17	11295	0	0	0
T19	1321	0	0	0
T20	87123	0	0	0
T21	36222	0	0	0
T22	0	67	0	0
T27	0	41	0	0
T28	0	39	0	0
T48	0	18	0	0
T80	26205	0	0	0
T91	0	37	0	0
T92	0	55	0	0
T93	0	45	0	0

gen_chk_digest_unmasked.StateZeroInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	482341611	0	0
T1	2517	2017	0	0
T2	2527	2033	0	0
T3	42818	42721	0	0
T4	2559	2405	0	0
T12	3035	2407	0	0
T13	665515	523781	0	0
T14	132067	92327	0	0
T15	6666	4967	0	0
T18	1132	1045	0	0
T19	1321	1236	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	567007961	0	0
T1	2517	2441	0	0
T2	2527	2429	0	0
T3	42818	42730	0	0
T4	2559	2405	0	0
T12	3035	2954	0	0
T13	665515	665440	0	0
T14	132067	131972	0	0
T15	6666	6605	0	0
T18	1132	1045	0	0
T19	1321	1236	0	0

Line Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
TOTAL		82	80	97.56
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	184	5	5	100.00
ALWAYS	198	3	3	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	207	6	6	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
ALWAYS	227	3	3	100.00
ALWAYS	237	38	38	100.00
ALWAYS	332	3	3	100.00
ALWAYS	349	12	10	83.33

137                       logic round_count_error, msg_count_error;
138        1/1            assign count_error_o =  round_count_error | msg_count_error;
           Tests:       T1 T2 T3 
139                     
140                       logic sha3_state_error;
141                       logic keccak_round_state_error;
142                       logic sha3pad_state_error;
143                     
144        1/1            assign sparse_fsm_error_o = sha3_state_error | keccak_round_state_error | sha3pad_state_error;
           Tests:       T1 T2 T3 
145                     
146                       // Keccak rst_storage is asserted unexpectedly
147                       logic keccak_storage_rst_error;
148        1/1            assign keccak_storage_rst_error_o = keccak_storage_rst_error;
           Tests:       T1 T2 T3 
149                     
150                       /////////////////
151                       // Connections //
152                       /////////////////
153                     
154                       logic                       keccak_valid;
155                       logic [KeccakMsgAddrW-1:0]  keccak_addr;
156                       logic [MsgWidth-1:0]        keccak_data [Share];
157                       logic                       keccak_ready;
158                     
159                       // Keccak round run signal can be controlled by sha3pad and also by software
160                       // after all message feeding is done. it is mainly used for sponge squeezing
161                       // operation after absorbing is completed when output length is longer than
162                       // the block size.
163                       logic keccak_run, sha3pad_keccak_run, sw_keccak_run;
164                       logic keccak_run_req_d, keccak_run_req_q;
165                       logic keccak_triggered_d, keccak_triggered_q;
166                       logic keccak_complete;
167                     
168                       // Announce that we want to run the Keccak core and tell other blocks to go
169                       // quiet. Keep holding the REQ until the Keccak core is done with the
170                       // processing. The keccak_complete signal is received once the Keccak core
171                       // is back in the Idle state and again susceptible to keccak_run.
172        1/1            assign run_req_o = keccak_run_req_d;
           Tests:       T1 T2 T3 
173        1/1            assign keccak_run_req_d =
           Tests:       T1 T2 T3 
174                           sha3pad_keccak_run || sw_keccak_run ? 1'b 1 :
175                           keccak_complete                     ? 1'b 0 : keccak_run_req_q;
176                     
177                       // Trigger the Keccak engine with a single pulse upon receiving the ACK.
178        1/1            assign keccak_run = run_req_o & run_ack_i & ~keccak_triggered_q;
           Tests:       T1 T2 T3 
179        1/1            assign keccak_triggered_d =
           Tests:       T1 T2 T3 
180                           keccak_run      ? 1'b 1 :
181                           keccak_complete ? 1'b 0 : keccak_triggered_q;
182                     
183                       always_ff @(posedge clk_i or negedge rst_ni) begin
184        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
185        1/1                keccak_run_req_q <= 1'b 0;
           Tests:       T1 T2 T3 
186        1/1                keccak_triggered_q <= 1'b 0;
           Tests:       T1 T2 T3 
187                         end else begin
188        1/1                keccak_run_req_q <= keccak_run_req_d;
           Tests:       T1 T2 T3 
189        1/1                keccak_triggered_q <= keccak_triggered_d;
           Tests:       T1 T2 T3 
190                         end
191                       end
192                     
193                       // Absorb pulse output : used to generate interrupts
194                       // Latch absorbed signal as kmac_keymgr asserts `CmdDone` when it sees
195                       // `absorbed` signal. When this signal goes out, the state is still in
196                       // `StAbsorb`. Next state is `StSqueeze`.
197                       always_ff @(posedge clk_i or negedge rst_ni) begin
198        2/2              if (!rst_ni) absorbed_o <= prim_mubi_pkg::MuBi4False;
           Tests:       T1 T2 T3  | T1 T2 T3 
199        1/1              else         absorbed_o <= absorbed;
           Tests:       T1 T2 T3 
200                       end
201                     
202                       // Squeezing output
203        1/1            assign squeezing_o = squeezing;
           Tests:       T1 T2 T3 
204                     
205                       // processing
206                       always_ff @(posedge clk_i or negedge rst_ni) begin
207        2/2              if (!rst_ni)        processing <= 1'b 0;
           Tests:       T1 T2 T3  | T1 T2 T3 
208        2/2              else if (process_i) processing <= 1'b 1;
           Tests:       T1 T2 T3  | T1 T2 T3 
209        1/1              else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
           Tests:       T1 T2 T3 
210        1/1                processing <= 1'b 0;
           Tests:       T1 T2 T3 
211                         end
                        MISSING_ELSE
212                       end
213                     
214        1/1            assign block_processed_o = keccak_complete;
           Tests:       T1 T2 T3 
215                     
216                       // State connection
217        1/1            assign state_valid_o = state_valid;
           Tests:       T1 T2 T3 
218        1/1            assign state_o = state_guarded;
           Tests:       T1 T2 T3 
219                     
220        1/1            assign sha3_fsm_o = sparse2logic(st);
           Tests:       T1 T2 T3 
221                     
222                       ///////////////////
223                       // State Machine //
224                       ///////////////////
225                     
226                       // State Register
227        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse):
227.1                   `ifdef SIMULATION                                   
227.2                       prim_sparse_fsm_flop #(                           
227.3                         .StateEnumT(sha3_st_sparse_e),                            
227.4                         .Width($bits(sha3_st_sparse_e)),                          
227.5                         .ResetValue($bits(sha3_st_sparse_e)'(StIdle_sparse)),          
227.6                         .EnableAlertTriggerSVA(1), 
227.7                         .CustomForceName("st")          
227.8                       ) u_state_regs (                                        
227.9                         .clk_i   ( clk_i   ),                           
227.10                        .rst_ni  ( rst_ni ),                           
227.11                        .state_i ( st_d     ),                           
227.12                        .state_o (         )                            
227.13                      );                                                
227.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
227.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
227.16     1/1                st <= StIdle_sparse;                                
           Tests:       T1 T2 T3 
227.17                      end else begin                                    
227.18     1/1                st <= st_d;                                     
           Tests:       T1 T2 T3 
227.19                      end                                               
227.20                    end  
227.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (st === u_state_regs.state_o))       
227.22                      else begin                                                                           
227.23                        `ifdef UVM                                                                               
227.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
227.25                                              "../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv", 227, "", 1);                                
227.26                  `else                                                                                    
227.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
227.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
227.29                  `endif                                                              
227.30                      end 
227.31                    `else                                               
227.32                      prim_sparse_fsm_flop #(                           
227.33                        .StateEnumT(sha3_st_sparse_e),                            
227.34                        .Width($bits(sha3_st_sparse_e)),                          
227.35                        .ResetValue($bits(sha3_st_sparse_e)'(StIdle_sparse)),          
227.36                        .EnableAlertTriggerSVA(1)  
227.37                      ) u_state_regs (                                        
227.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
227.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
227.40                        .state_i ( st_d     ),                           
227.41                        .state_o ( st     )                            
227.42                      );                                                
227.43                    `endif228                     
229                     
230                       // Next State and Output Logic
231                       // Mainly the FSM controls the input signal access
232                       // StIdle:    only start_i signal is allowed
233                       // StAbsorb:  only process_i signal is allowed
234                       // StSqueeze: only run_i, done_i signal is allowed
235                     
236                       always_comb begin
237        1/1              st_d = st;
           Tests:       T1 T2 T3 
238                     
239                         // default output values
240        1/1              keccak_start = 1'b 0;
           Tests:       T1 T2 T3 
241        1/1              keccak_process = 1'b 0;
           Tests:       T1 T2 T3 
242        1/1              sw_keccak_run = 1'b 0;
           Tests:       T1 T2 T3 
243        1/1              keccak_done = prim_mubi_pkg::MuBi4False;
           Tests:       T1 T2 T3 
244                     
245        1/1              squeezing = 1'b 0;
           Tests:       T1 T2 T3 
246                     
247        1/1              state_valid = 1'b 0;
           Tests:       T1 T2 T3 
248        1/1              mux_sel = MuxGuard ;
           Tests:       T1 T2 T3 
249                     
250        1/1              sha3_state_error = 1'b 0;
           Tests:       T1 T2 T3 
251                     
252        1/1              unique case (st)
           Tests:       T1 T2 T3 
253                           StIdle_sparse: begin
254        1/1                  if (start_i) begin
           Tests:       T1 T2 T3 
255        1/1                    st_d = StAbsorb_sparse;
           Tests:       T1 T2 T3 
256                     
257        1/1                    keccak_start = 1'b 1;
           Tests:       T1 T2 T3 
258                             end else begin
259        1/1                    st_d = StIdle_sparse;
           Tests:       T1 T2 T3 
260                             end
261                           end
262                     
263                           StAbsorb_sparse: begin
264        1/1                  if (process_i && !processing) begin
           Tests:       T1 T2 T3 
265        1/1                    st_d = StAbsorb_sparse;
           Tests:       T1 T2 T3 
266                     
267        1/1                    keccak_process = 1'b 1;
           Tests:       T1 T2 T3 
268        1/1                  end else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
           Tests:       T1 T2 T3 
269        1/1                    st_d = StSqueeze_sparse;
           Tests:       T1 T2 T3 
270                             end else begin
271        1/1                    st_d = StAbsorb_sparse;
           Tests:       T1 T2 T3 
272                             end
273                           end
274                     
275                           StSqueeze_sparse: begin
276        1/1                  state_valid = 1'b 1;
           Tests:       T1 T2 T3 
277        1/1                  mux_sel = MuxRelease; // Expose state to register interface
           Tests:       T1 T2 T3 
278                     
279        1/1                  squeezing = 1'b 1;
           Tests:       T1 T2 T3 
280                     
281        1/1                  if (run_i) begin
           Tests:       T1 T2 T3 
282        1/1                    st_d = StManualRun_sparse;
           Tests:       T13 T14 T5 
283                     
284        1/1                    sw_keccak_run = 1'b 1;
           Tests:       T13 T14 T5 
285        1/1                  end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
           Tests:       T1 T2 T3 
286        1/1                    st_d = StFlush_sparse;
           Tests:       T1 T2 T3 
287                     
288        1/1                    keccak_done = done_i;
           Tests:       T1 T2 T3 
289                             end else begin
290        1/1                    st_d = StSqueeze_sparse;
           Tests:       T1 T2 T12 
291                             end
292                           end
293                     
294                           StManualRun_sparse: begin
295        1/1                  if (keccak_complete) begin
           Tests:       T13 T14 T5 
296        1/1                    st_d = StSqueeze_sparse;
           Tests:       T13 T14 T5 
297                             end else begin
298        1/1                    st_d = StManualRun_sparse;
           Tests:       T13 T14 T5 
299                             end
300                           end
301                     
302                           StFlush_sparse: begin
303        1/1                  st_d = StIdle_sparse;
           Tests:       T1 T2 T3 
304                           end
305                     
306                           StTerminalError_sparse: begin
307                             //this state is terminal
308        1/1                  st_d = StTerminalError_sparse;
           Tests:       T4 T5 T6 
309        1/1                  sha3_state_error = 1'b 1;
           Tests:       T4 T5 T6 
310                           end
311                     
312                           default: begin
313                             st_d = StTerminalError_sparse;
314                             sha3_state_error = 1'b 1;
315                           end
316                         endcase
317                     
318                         // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC
319                         // Unconditionally jump into the terminal error state
320                         // if the life cycle controller triggers an escalation.
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                st_d = StTerminalError_sparse;
           Tests:       T4 T5 T6 
323                         end
                        MISSING_ELSE
324                       end
325                     
326                       //////////////
327                       // Datapath //
328                       //////////////
329                     
330                       // State --> Digest output
331                       always_comb begin : state_guarded_mux
332        1/1              unique case (mux_sel)
           Tests:       T1 T2 T3 
333        1/1                MuxGuard:   state_guarded = '{default: '0};
           Tests:       T1 T2 T3 
334        1/1                MuxRelease: state_guarded = state;
           Tests:       T1 T2 T3 
335                           default:    state_guarded = '{default: '0}; // a valid, safe output
336                         endcase
337                       end
338                     
339                     
340                       // Error Detecting
341                       // ErrSha3SwControl:
342                       //   info[ 0]: start_i set
343                       //   info[ 1]: process_i set
344                       //   info[ 2]: run_i set
345                       //   info[ 3]: done_i set
346                       //  - Sw set process_i, run_i, done_i without start_i
347                     
348                       always_comb begin
349        1/1              error_o = '{valid: 1'b0, code: ErrNone, info: '0};
           Tests:       T1 T2 T3 
350                     
351        1/1              unique case (st)
           Tests:       T1 T2 T3 
352                           StIdle_sparse: begin
353        1/1                  if (process_i || run_i ||
           Tests:       T1 T2 T3 
354                               prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
355        1/1                    error_o = '{
           Tests:       T14 T27 T34 
356                                 valid: 1'b 1,
357                                 code: ErrSha3SwControl,
358                                 info: 24'({done_i, run_i, process_i, start_i})
359                               };
360                             end
                        MISSING_ELSE
361                           end
362                     
363                           StAbsorb_sparse: begin
364        1/1                  if (start_i || run_i || prim_mubi_pkg::mubi4_test_true_loose(done_i)
           Tests:       T1 T2 T3 
365                               || (process_i && processing)) begin
366        1/1                    error_o = '{
           Tests:       T14 T27 T34 
367                                 valid: 1'b 1,
368                                 code: ErrSha3SwControl,
369                                 info: 24'({done_i, run_i, process_i, start_i})
370                               };
371                             end
                        MISSING_ELSE
372                           end
373                     
374                           StSqueeze_sparse: begin
375        1/1                  if (start_i || process_i) begin
           Tests:       T1 T2 T3 
376        0/1     ==>            error_o = '{
377                                 valid: 1'b 1,
378                                 code: ErrSha3SwControl,
379                                 info: 24'({done_i, run_i, process_i, start_i})
380                               };
381                             end
                        MISSING_ELSE
382                           end
383                     
384                           StManualRun_sparse: begin
385        1/1                  if (start_i || process_i || run_i ||
           Tests:       T13 T14 T5 
386                               prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
387        1/1                    error_o = '{
           Tests:       T14 T27 T34 
388                                 valid: 1'b 1,
389                                 code: ErrSha3SwControl,
390                                 info: 24'({done_i, run_i, process_i, start_i})
391                               };
392                             end
                        MISSING_ELSE
393                           end
394                     
395                           StFlush_sparse: begin
396        1/1                  if (start_i || process_i || run_i ||
           Tests:       T1 T2 T3 
397                               prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
398        0/1     ==>            error_o = '{
399                                 valid: 1'b 1,
400                                 code: ErrSha3SwControl,
401                                 info: 24'({done_i, run_i, process_i, start_i})
402                               };
403                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3

	Total	Covered	Percent
Conditions	27	24	88.89
Logical	27	24	88.89
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       144
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T9,T10,T11
0	1	0	Covered	T9,T10,T11
1	0	0	Covered	T9,T10,T11

 LINE       173
 EXPRESSION ((sha3pad_keccak_run || sw_keccak_run) ? 1'b1 : (keccak_complete ? 1'b0 : keccak_run_req_q))
             ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       173
 SUB-EXPRESSION (sha3pad_keccak_run || sw_keccak_run)
                 ---------1--------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T5
1	0	Covered	T1,T2,T3

 LINE       173
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_run_req_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (run_req_o & run_ack_i & ((~keccak_triggered_q)))
             ----1----   ----2----   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       179
 EXPRESSION (keccak_run ? 1'b1 : (keccak_complete ? 1'b0 : keccak_triggered_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       179
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_triggered_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       264
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	255	Covered	T1,T2,T3
StFlush_sparse	286	Covered	T1,T2,T3
StIdle_sparse	259	Covered	T1,T2,T3
StManualRun_sparse	282	Covered	T13,T14,T5
StSqueeze_sparse	269	Covered	T1,T2,T3
StTerminalError_sparse	308	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
StAbsorb_sparse->StSqueeze_sparse	269	Covered	T1,T2,T3
StAbsorb_sparse->StTerminalError_sparse	322	Covered	T4,T6,T39
StFlush_sparse->StIdle_sparse	303	Covered	T1,T2,T3
StFlush_sparse->StTerminalError_sparse	322	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StIdle_sparse->StAbsorb_sparse	255	Covered	T1,T2,T3
StIdle_sparse->StTerminalError_sparse	322	Covered	T5,T9,T10
StManualRun_sparse->StSqueeze_sparse	296	Covered	T13,T14,T5
StManualRun_sparse->StTerminalError_sparse	322	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StSqueeze_sparse->StFlush_sparse	286	Covered	T1,T2,T3
StSqueeze_sparse->StManualRun_sparse	282	Covered	T13,T14,T5
StSqueeze_sparse->StTerminalError_sparse	322	Covered	T59,T60,T61

---

Branch Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
Branches		45	42	93.33
TERNARY	173	3	3	100.00
TERNARY	179	3	3	100.00
IF	184	2	2	100.00
IF	198	2	2	100.00
IF	207	4	4	100.00
IF	227	2	2	100.00
CASE	252	13	13	100.00
IF	321	2	2	100.00
CASE	332	3	2	66.67
CASE	351	11	9	81.82

173          assign keccak_run_req_d =
                                      
174              sha3pad_keccak_run || sw_keccak_run ? 1'b 1 :
                                                     -1-  
                                                     ==>  
175              keccak_complete                     ? 1'b 0 : keccak_run_req_q;
                                                     -2-  
                                                     ==>  
                                                     ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

179          assign keccak_triggered_d =
                                        
180              keccak_run      ? 1'b 1 :
                                 -1-  
                                 ==>  
181              keccak_complete ? 1'b 0 : keccak_triggered_q;
                                 -2-  
                                 ==>  
                                 ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

184            if (!rst_ni) begin
               -1-  
185              keccak_run_req_q <= 1'b 0;
                 ==>
186              keccak_triggered_q <= 1'b 0;
187            end else begin
188              keccak_run_req_q <= keccak_run_req_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

198            if (!rst_ni) absorbed_o <= prim_mubi_pkg::MuBi4False;
               -1-  
               ==>
199            else         absorbed_o <= absorbed;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

207            if (!rst_ni)        processing <= 1'b 0;
               -1-  
               ==>
208            else if (process_i) processing <= 1'b 1;
                    -2-  
               ==>
209            else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
                    -3-  
210              processing <= 1'b 0;
                 ==>
211            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

227          `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse)
             -1-                                                                              
             ==>                                                                              
             ==>                                                                              

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

252            unique case (st)
                      -1-  
253              StIdle_sparse: begin
254                if (start_i) begin
                   -2-  
255                  st_d = StAbsorb_sparse;
                     ==>
256        
257                  keccak_start = 1'b 1;
258                end else begin
259                  st_d = StIdle_sparse;
                     ==>
260                end
261              end
262        
263              StAbsorb_sparse: begin
264                if (process_i && !processing) begin
                   -3-  
265                  st_d = StAbsorb_sparse;
                     ==>
266        
267                  keccak_process = 1'b 1;
268                end else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
                            -4-  
269                  st_d = StSqueeze_sparse;
                     ==>
270                end else begin
271                  st_d = StAbsorb_sparse;
                     ==>
272                end
273              end
274        
275              StSqueeze_sparse: begin
276                state_valid = 1'b 1;
277                mux_sel = MuxRelease; // Expose state to register interface
278        
279                squeezing = 1'b 1;
280        
281                if (run_i) begin
                   -5-  
282                  st_d = StManualRun_sparse;
                     ==>
283        
284                  sw_keccak_run = 1'b 1;
285                end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
                            -6-  
286                  st_d = StFlush_sparse;
                     ==>
287        
288                  keccak_done = done_i;
289                end else begin
290                  st_d = StSqueeze_sparse;
                     ==>
291                end
292              end
293        
294              StManualRun_sparse: begin
295                if (keccak_complete) begin
                   -7-  
296                  st_d = StSqueeze_sparse;
                     ==>
297                end else begin
298                  st_d = StManualRun_sparse;
                     ==>
299                end
300              end
301        
302              StFlush_sparse: begin
303                st_d = StIdle_sparse;
                   ==>
304              end
305        
306              StTerminalError_sparse: begin
307                //this state is terminal
308                st_d = StTerminalError_sparse;
                   ==>
309                sha3_state_error = 1'b 1;
310              end
311        
312              default: begin
313                st_d = StTerminalError_sparse;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle_sparse	0	-	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	1	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	1	-	-	Covered	T13,T14,T5
StSqueeze_sparse	-	-	-	0	1	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	0	0	-	Covered	T1,T2,T12
StManualRun_sparse	-	-	-	-	-	1	Covered	T13,T14,T5
StManualRun_sparse	-	-	-	-	-	0	Covered	T13,T14,T5
StFlush_sparse	-	-	-	-	-	-	Covered	T1,T2,T3
StTerminalError_sparse	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	Covered	T9,T10,T11

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
               -1-  
322              st_d = StTerminalError_sparse;
                 ==>
323            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

332            unique case (mux_sel)
                      -1-  
333              MuxGuard:   state_guarded = '{default: '0};
                 ==>
334              MuxRelease: state_guarded = state;
                 ==>
335              default:    state_guarded = '{default: '0}; // a valid, safe output
                 ==>

Branches:

-1-	Status	Tests
MuxGuard	Covered	T1,T2,T3
MuxRelease	Covered	T1,T2,T3
default	Not Covered

351            unique case (st)
                      -1-  
352              StIdle_sparse: begin
353                if (process_i || run_i ||
                   -2-  
354                  prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
355                  error_o = '{
                     ==>
356                    valid: 1'b 1,
357                    code: ErrSha3SwControl,
358                    info: 24'({done_i, run_i, process_i, start_i})
359                  };
360                end
                   MISSING_ELSE
                   ==>
361              end
362        
363              StAbsorb_sparse: begin
364                if (start_i || run_i || prim_mubi_pkg::mubi4_test_true_loose(done_i)
                   -3-  
365                  || (process_i && processing)) begin
366                  error_o = '{
                     ==>
367                    valid: 1'b 1,
368                    code: ErrSha3SwControl,
369                    info: 24'({done_i, run_i, process_i, start_i})
370                  };
371                end
                   MISSING_ELSE
                   ==>
372              end
373        
374              StSqueeze_sparse: begin
375                if (start_i || process_i) begin
                   -4-  
376                  error_o = '{
                     ==>
377                    valid: 1'b 1,
378                    code: ErrSha3SwControl,
379                    info: 24'({done_i, run_i, process_i, start_i})
380                  };
381                end
                   MISSING_ELSE
                   ==>
382              end
383        
384              StManualRun_sparse: begin
385                if (start_i || process_i || run_i ||
                   -5-  
386                  prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
387                  error_o = '{
                     ==>
388                    valid: 1'b 1,
389                    code: ErrSha3SwControl,
390                    info: 24'({done_i, run_i, process_i, start_i})
391                  };
392                end
                   MISSING_ELSE
                   ==>
393              end
394        
395              StFlush_sparse: begin
396                if (start_i || process_i || run_i ||
                   -6-  
397                  prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
398                  error_o = '{
                     ==>
399                    valid: 1'b 1,
400                    code: ErrSha3SwControl,
401                    info: 24'({done_i, run_i, process_i, start_i})
402                  };
403                end
                   MISSING_ELSE
                   ==>
404              end
405        
406              default: begin
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Covered	T14,T27,T34
StIdle_sparse	0	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	Covered	T14,T27,T34
StAbsorb_sparse	-	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Covered	T1,T2,T3
StManualRun_sparse	-	-	-	1	-	Covered	T14,T27,T34
StManualRun_sparse	-	-	-	0	-	Covered	T13,T5,T48
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sha3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrDetection_A	567132835	8158494	0	0
FsmKnown_A	567019212	566898845	0	0
KeccakIdleWhenNoRunHs_A	567132835	21000616	0	0
MuxSelKnown_A	567132835	567007961	0	0
SwRunInSqueezing_a	567132835	120486	0	0
gen_chk_digest_unmasked.StateZeroInvalid_A	567132835	482341611	0	0
u_state_regs_A	567132835	567007961	0	0

ErrDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	8158494	0	0
T5	13685	0	0	0
T14	132067	82202	0	0
T15	6666	0	0	0
T16	2469	0	0	0
T17	11295	0	0	0
T19	1321	0	0	0
T20	87123	0	0	0
T21	36222	0	0	0
T27	0	69290	0	0
T34	0	116395	0	0
T35	86217	0	0	0
T80	26205	0	0	0
T84	0	159840	0	0
T85	0	459719	0	0
T86	0	115341	0	0
T87	0	71172	0	0
T88	0	268992	0	0
T89	0	261818	0	0
T90	0	23492	0	0

FsmKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567019212	566898845	0	0
T1	2517	2441	0	0
T2	2527	2429	0	0
T3	42818	42730	0	0
T4	2559	2405	0	0
T12	3035	2954	0	0
T13	665515	665440	0	0
T14	132067	131972	0	0
T15	6666	6605	0	0
T18	1132	1045	0	0
T19	1321	1236	0	0

KeccakIdleWhenNoRunHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	21000616	0	0
T1	2517	240	0	0
T2	2527	240	0	0
T3	42818	648	0	0
T4	2559	49	0	0
T12	3035	240	0	0
T13	665515	10944	0	0
T14	132067	11616	0	0
T15	6666	240	0	0
T16	0	240	0	0
T17	0	264	0	0
T18	1132	0	0	0
T19	1321	0	0	0

MuxSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	567007961	0	0
T1	2517	2441	0	0
T2	2527	2429	0	0
T3	42818	42730	0	0
T4	2559	2405	0	0
T12	3035	2954	0	0
T13	665515	665440	0	0
T14	132067	131972	0	0
T15	6666	6605	0	0
T18	1132	1045	0	0
T19	1321	1236	0	0

SwRunInSqueezing_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	120486	0	0
T5	13685	4	0	0
T13	665515	117	0	0
T14	132067	161	0	0
T15	6666	0	0	0
T16	2469	0	0	0
T17	11295	0	0	0
T19	1321	0	0	0
T20	87123	0	0	0
T21	36222	0	0	0
T22	0	67	0	0
T27	0	41	0	0
T28	0	39	0	0
T48	0	18	0	0
T80	26205	0	0	0
T91	0	37	0	0
T92	0	55	0	0
T93	0	45	0	0

gen_chk_digest_unmasked.StateZeroInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	482341611	0	0
T1	2517	2017	0	0
T2	2527	2033	0	0
T3	42818	42721	0	0
T4	2559	2405	0	0
T12	3035	2407	0	0
T13	665515	523781	0	0
T14	132067	92327	0	0
T15	6666	4967	0	0
T18	1132	1045	0	0
T19	1321	1236	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567132835	567007961	0	0
T1	2517	2441	0	0
T2	2527	2429	0	0
T3	42818	42730	0	0
T4	2559	2405	0	0
T12	3035	2954	0	0
T13	665515	665440	0	0
T14	132067	131972	0	0
T15	6666	6605	0	0
T18	1132	1045	0	0
T19	1321	1236	0	0