Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	568441050	4683	0	0
entropy_period_rd_A	568441050	1245	0	0
intr_enable_rd_A	568441050	1720	0	0
prefix_0_rd_A	568441050	1245	0	0
prefix_10_rd_A	568441050	1215	0	0
prefix_1_rd_A	568441050	1158	0	0
prefix_2_rd_A	568441050	1174	0	0
prefix_3_rd_A	568441050	1225	0	0
prefix_4_rd_A	568441050	1198	0	0
prefix_5_rd_A	568441050	1177	0	0
prefix_6_rd_A	568441050	1343	0	0
prefix_7_rd_A	568441050	1170	0	0
prefix_8_rd_A	568441050	1110	0	0
prefix_9_rd_A	568441050	1182	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	4683	0	0
T43	106588	0	0	0
T56	145819	2160	0	0
T57	0	84	0	0
T58	0	2	0	0
T86	167711	0	0	0
T113	0	2	0	0
T114	0	2	0	0
T115	0	1	0	0
T118	0	106	0	0
T120	0	235	0	0
T125	0	2	0	0
T126	0	3	0	0
T127	12454	0	0	0
T128	54729	0	0	0
T129	297425	0	0	0
T130	85677	0	0	0
T131	237709	0	0	0
T132	216530	0	0	0
T133	4293	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1245	0	0
T99	13633	49	0	0
T106	3812	2	0	0
T108	11121	52	0	0
T114	12778	55	0	0
T115	10879	51	0	0
T153	3475	22	0	0
T154	2105	3	0	0
T155	5889	19	0	0
T156	10626	20	0	0
T157	23219	104	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1720	0	0
T99	13633	67	0	0
T106	3812	5	0	0
T108	11121	77	0	0
T114	12778	72	0	0
T115	10879	37	0	0
T153	3475	15	0	0
T154	2105	2	0	0
T155	5889	3	0	0
T156	10626	12	0	0
T158	1206	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1245	0	0
T99	13633	16	0	0
T106	3812	18	0	0
T108	11121	63	0	0
T114	12778	35	0	0
T115	10879	28	0	0
T154	2105	1	0	0
T155	5889	28	0	0
T156	10626	55	0	0
T157	23219	108	0	0
T159	1766	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1215	0	0
T99	13633	25	0	0
T106	3812	3	0	0
T108	11121	47	0	0
T114	12778	47	0	0
T115	10879	32	0	0
T153	3475	7	0	0
T155	5889	2	0	0
T156	10626	15	0	0
T157	23219	204	0	0
T159	1766	5	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1158	0	0
T99	13633	32	0	0
T106	3812	11	0	0
T108	11121	50	0	0
T114	12778	46	0	0
T115	10879	9	0	0
T153	3475	9	0	0
T154	2105	4	0	0
T155	5889	20	0	0
T156	10626	7	0	0
T157	23219	137	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1174	0	0
T99	13633	25	0	0
T106	3812	18	0	0
T108	11121	47	0	0
T114	12778	59	0	0
T115	10879	28	0	0
T136	13974	20	0	0
T153	3475	8	0	0
T155	5889	17	0	0
T156	10626	22	0	0
T157	23219	125	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1225	0	0
T99	13633	35	0	0
T106	3812	1	0	0
T108	11121	48	0	0
T114	12778	41	0	0
T115	10879	26	0	0
T153	3475	1	0	0
T155	5889	37	0	0
T156	10626	87	0	0
T157	23219	122	0	0
T159	1766	7	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1198	0	0
T99	13633	20	0	0
T106	3812	2	0	0
T108	11121	58	0	0
T114	12778	29	0	0
T115	10879	27	0	0
T153	3475	2	0	0
T154	2105	8	0	0
T155	5889	11	0	0
T156	10626	38	0	0
T157	23219	144	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1177	0	0
T57	6969	2	0	0
T99	13633	39	0	0
T106	3812	6	0	0
T108	11121	31	0	0
T114	12778	29	0	0
T115	10879	19	0	0
T153	3475	15	0	0
T154	2105	6	0	0
T155	5889	8	0	0
T156	10626	57	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1343	0	0
T99	13633	33	0	0
T106	3812	8	0	0
T108	11121	38	0	0
T114	12778	34	0	0
T115	10879	11	0	0
T153	3475	9	0	0
T154	2105	8	0	0
T155	5889	9	0	0
T156	10626	29	0	0
T157	23219	102	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1170	0	0
T99	13633	37	0	0
T108	11121	60	0	0
T114	12778	51	0	0
T115	10879	27	0	0
T153	3475	5	0	0
T154	2105	2	0	0
T155	5889	19	0	0
T156	10626	27	0	0
T157	23219	142	0	0
T159	1766	10	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1110	0	0
T57	6969	2	0	0
T99	13633	36	0	0
T106	3812	7	0	0
T108	11121	42	0	0
T114	12778	40	0	0
T115	10879	10	0	0
T153	3475	2	0	0
T154	2105	8	0	0
T155	5889	27	0	0
T156	10626	57	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568441050	1182	0	0
T99	13633	9	0	0
T106	3812	4	0	0
T108	11121	50	0	0
T114	12778	35	0	0
T115	10879	14	0	0
T153	3475	11	0	0
T154	2105	5	0	0
T155	5889	24	0	0
T156	10626	52	0	0
T157	23219	115	0	0