Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14412118	1			T1	119		T2	68		T12	1011
all_values[1]	14412118	1			T1	119		T2	68		T12	1011
all_values[2]	14412118	1			T1	119		T2	68		T12	1011

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

442590

1

T1

182

T2

80

T12

22

auto[1]

42793764

1

T1

175

T2

124

T12

3011

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43023984

1

T1

342

T2

186

T12

2682

auto[1]

212370

1

T1

15

T2

18

T12

351

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	136031	1			T1	59		T2	62		T12	5
all_values[0]	auto[0]	auto[1]	1272	1			T1	4		T2	6		T12	6
all_values[0]	auto[1]	auto[0]	14205297	1			T1	55		T12	889		T13	1278
all_values[0]	auto[1]	auto[1]	69518	1			T1	1		T12	111		T13	9
all_values[1]	auto[0]	auto[0]	170366	1			T13	356		T15	4		T16	8
all_values[1]	auto[0]	auto[1]	1011	1			T13	2		T15	2		T16	4
all_values[1]	auto[1]	auto[0]	14170962	1			T1	114		T2	62		T12	894
all_values[1]	auto[1]	auto[1]	69779	1			T1	5		T2	6		T12	117
all_values[2]	auto[0]	auto[0]	132958	1			T1	114		T2	8		T12	5
all_values[2]	auto[0]	auto[1]	952	1			T1	5		T2	4		T12	6
all_values[2]	auto[1]	auto[0]	14208370	1			T2	54		T12	889		T13	1114
all_values[2]	auto[1]	auto[1]	69838	1			T2	2		T12	111		T13	8