Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54486 |
1 |
|
|
T1 |
2 |
|
T2 |
6 |
|
T12 |
146 |
auto[1] |
52864 |
1 |
|
|
T1 |
4 |
|
T13 |
24 |
|
T16 |
272 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
26961 |
1 |
|
|
T12 |
37 |
|
T13 |
10 |
|
T4 |
2 |
lower_val |
26529 |
1 |
|
|
T2 |
3 |
|
T12 |
44 |
|
T13 |
9 |
zero_val |
876 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T12 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
53888 |
1 |
|
|
T2 |
2 |
|
T12 |
88 |
|
T13 |
12 |
lower_val |
53462 |
1 |
|
|
T1 |
6 |
|
T2 |
4 |
|
T12 |
58 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6792 |
1 |
|
|
T12 |
21 |
|
T13 |
1 |
|
T4 |
1 |
higher_val |
higher_val |
auto[1] |
6717 |
1 |
|
|
T13 |
1 |
|
T16 |
28 |
|
T77 |
49 |
higher_val |
lower_val |
auto[0] |
6645 |
1 |
|
|
T12 |
16 |
|
T4 |
1 |
|
T15 |
1 |
higher_val |
lower_val |
auto[1] |
6807 |
1 |
|
|
T13 |
8 |
|
T16 |
35 |
|
T77 |
36 |
lower_val |
higher_val |
auto[0] |
6854 |
1 |
|
|
T2 |
1 |
|
T12 |
25 |
|
T4 |
7 |
lower_val |
higher_val |
auto[1] |
6397 |
1 |
|
|
T13 |
6 |
|
T16 |
22 |
|
T48 |
1 |
lower_val |
lower_val |
auto[0] |
6701 |
1 |
|
|
T2 |
2 |
|
T12 |
19 |
|
T4 |
1 |
lower_val |
lower_val |
auto[1] |
6577 |
1 |
|
|
T13 |
3 |
|
T16 |
44 |
|
T48 |
1 |
zero_val |
higher_val |
auto[0] |
343 |
1 |
|
|
T13 |
1 |
|
T15 |
1 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
98 |
1 |
|
|
T77 |
1 |
|
T151 |
1 |
|
T37 |
2 |
zero_val |
lower_val |
auto[0] |
347 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
88 |
1 |
|
|
T77 |
1 |
|
T86 |
2 |
|
T151 |
1 |