Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14412118	1			T1	119		T2	68		T12	1011
all_pins[1]	14412118	1			T1	119		T2	68		T12	1011
all_pins[2]	14412118	1			T1	119		T2	68		T12	1011

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42898491	1			T1	356		T2	204		T12	2922
values[0x1]	337863	1			T1	1		T12	111		T13	9
transitions[0x0=>0x1]	336208	1			T1	1		T12	111		T13	9
transitions[0x1=>0x0]	336235	1			T1	1		T12	111		T13	9

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14342600	1			T1	118		T2	68		T12	900
all_pins[0]	values[0x1]	69518	1			T1	1		T12	111		T13	9
all_pins[0]	transitions[0x0=>0x1]	69508	1			T1	1		T12	111		T13	9
all_pins[0]	transitions[0x1=>0x0]	66	1			T53	5		T163	3		T164	2
all_pins[1]	values[0x0]	14412042	1			T1	119		T2	68		T12	1011
all_pins[1]	values[0x1]	76	1			T53	5		T163	3		T164	2
all_pins[1]	transitions[0x0=>0x1]	64	1			T53	5		T163	3		T164	2
all_pins[1]	transitions[0x1=>0x0]	268257	1			T38	9644		T54	198		T39	1707
all_pins[2]	values[0x0]	14143849	1			T1	119		T2	68		T12	1011
all_pins[2]	values[0x1]	268269	1			T38	9644		T54	198		T39	1707
all_pins[2]	transitions[0x0=>0x1]	266636	1			T38	9575		T54	198		T39	1695
all_pins[2]	transitions[0x1=>0x0]	67912	1			T1	1		T12	111		T13	9