Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	634	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5283	1			T13	2		T4	1		T21	7
len_601_800	12069	1			T13	2		T4	2		T31	1
len_401_600	8029	1			T4	1		T21	19		T38	25
len_201_400	3958	1			T13	1		T4	1		T31	1
len_65_200	6692	1			T49	44		T77	100		T75	65
len_min_for_xof_require_squeeze	71	1			T77	1		T51	1		T177	2
len_keccak_block_sizes[72]	81	1			T49	1		T75	2		T151	9
len_keccak_block_sizes[104]	65	1			T49	1		T77	2		T177	1
len_keccak_block_sizes[136]	70	1			T77	2		T39	1		T177	1
len_keccak_block_sizes[144]	39	1			T75	2		T42	1		T129	5
len_keccak_block_sizes[168]	28	1			T178	1		T42	1		T129	5
len_datapath_width	940	1			T1	3		T12	73		T15	3
len_2_63	14938	1			T2	3		T13	8		T4	7
len_1	46	1			T77	1		T75	1		T21	1