Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 281 1 T111 7 T114 7 T158 4
all_values[1] 281 1 T111 7 T114 7 T158 4
all_values[2] 281 1 T111 7 T114 7 T158 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 462 1 T111 13 T114 8 T158 8
auto[1] 381 1 T111 8 T114 13 T158 4


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 389 1 T111 7 T114 15 T158 4
auto[1] 454 1 T111 14 T114 6 T158 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 500 1 T111 10 T114 15 T158 8
auto[1] 343 1 T111 11 T114 6 T158 4


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 60 1 T111 1 T158 1 T159 3
all_values[0] auto[0] auto[0] auto[1] 23 1 T111 1 T158 1 T149 1
all_values[0] auto[0] auto[1] auto[0] 51 1 T114 4 T159 1 T160 1
all_values[0] auto[0] auto[1] auto[1] 31 1 T111 1 T158 1 T149 1
all_values[0] auto[1] auto[0] auto[1] 67 1 T111 3 T114 2 T158 1
all_values[0] auto[1] auto[1] auto[1] 49 1 T111 1 T114 1 T159 1
all_values[1] auto[0] auto[0] auto[0] 98 1 T111 2 T114 1 T158 2
all_values[1] auto[0] auto[1] auto[0] 72 1 T111 3 T114 3 T158 1
all_values[1] auto[1] auto[0] auto[1] 64 1 T111 1 T114 1 T158 1
all_values[1] auto[1] auto[1] auto[1] 47 1 T111 1 T114 2 T159 1
all_values[2] auto[0] auto[0] auto[0] 61 1 T111 1 T114 4 T159 3
all_values[2] auto[0] auto[0] auto[1] 27 1 T111 1 T149 2 T161 1
all_values[2] auto[0] auto[1] auto[0] 47 1 T114 3 T159 2 T160 1
all_values[2] auto[0] auto[1] auto[1] 30 1 T158 2 T160 1 T162 1
all_values[2] auto[1] auto[0] auto[1] 62 1 T111 3 T158 2 T149 2
all_values[2] auto[1] auto[1] auto[1] 54 1 T111 2 T159 2 T160 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%