Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40091214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

48913469

1

T1

438

T2

554

T3

173

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48775731	1			T1	347		T2	465		T3	90
values[0x0]	19493252	1			T1	152		T2	199		T3	47
values[0x1]	20735700	1			T1	176		T2	220		T3	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31149960	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

57854723

1

T1

497

T2

620

T3

181

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	328226	1			T1	2		T4	2		T17	1
valid_sources[0x01]	284463	1			T12	11		T18	40		T95	61
valid_sources[0x02]	281025	1			T1	2		T4	3		T17	1
valid_sources[0x03]	291773	1			T1	2		T18	52		T95	64
valid_sources[0x04]	281400	1			T1	1		T12	11		T17	3
valid_sources[0x05]	283939	1			T1	2		T4	1		T12	8
valid_sources[0x06]	282785	1			T1	4		T4	4		T12	1
valid_sources[0x07]	287701	1			T1	3		T12	5		T13	888
valid_sources[0x08]	346892	1			T1	1		T4	1		T12	1
valid_sources[0x09]	284118	1			T1	4		T4	2		T12	2
valid_sources[0x0a]	1168936	1			T1	1		T4	1		T12	3
valid_sources[0x0b]	282515	1			T1	3		T4	1		T18	30
valid_sources[0x0c]	423868	1			T1	2		T4	1		T12	13
valid_sources[0x0d]	306877	1			T1	3		T4	1		T17	5
valid_sources[0x0e]	400820	1			T1	2		T4	3		T12	2
valid_sources[0x0f]	280593	1			T1	3		T4	1		T17	1
valid_sources[0x10]	282356	1			T1	2		T4	2		T12	5
valid_sources[0x11]	374490	1			T1	2		T4	3		T12	1
valid_sources[0x12]	280182	1			T1	6		T17	1		T18	34
valid_sources[0x13]	409423	1			T4	2		T12	3		T17	4
valid_sources[0x14]	284028	1			T1	2		T4	1		T17	8
valid_sources[0x15]	304092	1			T1	4		T4	2		T12	4
valid_sources[0x16]	284986	1			T1	4		T4	1		T17	3
valid_sources[0x17]	281207	1			T1	2		T3	91		T12	2
valid_sources[0x18]	295174	1			T4	2		T12	1		T18	37
valid_sources[0x19]	285426	1			T1	3		T12	17		T18	36
valid_sources[0x1a]	283862	1			T1	3		T4	1		T17	4
valid_sources[0x1b]	499681	1			T1	3		T12	5		T17	1
valid_sources[0x1c]	287000	1			T1	4		T4	1		T12	11
valid_sources[0x1d]	283562	1			T1	6		T4	1		T12	9
valid_sources[0x1e]	292915	1			T1	3		T12	13		T18	35
valid_sources[0x1f]	281088	1			T1	2		T17	2		T18	37
valid_sources[0x20]	315951	1			T1	4		T4	2		T17	2
valid_sources[0x21]	283335	1			T1	3		T4	1		T12	8
valid_sources[0x22]	282276	1			T1	5		T4	1		T18	30
valid_sources[0x23]	282872	1			T1	6		T4	2		T12	15
valid_sources[0x24]	348446	1			T1	2		T4	1		T18	39
valid_sources[0x25]	451774	1			T1	1		T12	3		T18	33
valid_sources[0x26]	284320	1			T1	4		T4	2		T12	5
valid_sources[0x27]	281427	1			T1	3		T12	3		T18	37
valid_sources[0x28]	282776	1			T1	2		T4	3		T12	12
valid_sources[0x29]	292596	1			T1	5		T4	1		T17	5
valid_sources[0x2a]	494817	1			T17	2		T18	31		T95	67
valid_sources[0x2b]	281260	1			T1	1		T4	2		T18	47
valid_sources[0x2c]	279555	1			T1	4		T4	1		T12	6
valid_sources[0x2d]	407087	1			T1	2		T4	3		T17	5
valid_sources[0x2e]	283796	1			T1	2		T19	1		T4	1
valid_sources[0x2f]	282166	1			T1	3		T19	1		T4	2
valid_sources[0x30]	280828	1			T1	3		T12	7		T18	33
valid_sources[0x31]	286451	1			T1	1		T4	1		T17	3
valid_sources[0x32]	279783	1			T1	6		T19	1		T12	3
valid_sources[0x33]	310100	1			T1	1		T12	5		T17	4
valid_sources[0x34]	298456	1			T1	2		T12	9		T18	29
valid_sources[0x35]	311908	1			T1	3		T4	1		T49	1
valid_sources[0x36]	279181	1			T1	2		T4	2		T12	6
valid_sources[0x37]	282495	1			T1	4		T4	4		T17	1
valid_sources[0x38]	284987	1			T1	2		T4	5		T12	1
valid_sources[0x39]	281448	1			T1	4		T4	3		T12	7
valid_sources[0x3a]	286743	1			T1	3		T4	2		T12	1
valid_sources[0x3b]	282024	1			T1	1		T4	3		T17	1
valid_sources[0x3c]	285139	1			T1	5		T12	2		T17	7
valid_sources[0x3d]	283053	1			T1	2		T18	34		T95	59
valid_sources[0x3e]	282167	1			T1	3		T4	3		T12	3
valid_sources[0x3f]	281445	1			T1	1		T17	4		T18	35
valid_sources[0x40]	286978	1			T1	11		T4	3		T17	2
valid_sources[0x41]	281589	1			T1	3		T18	38		T95	69
valid_sources[0x42]	487429	1			T1	1		T4	1		T18	41
valid_sources[0x43]	285412	1			T4	1		T12	3		T17	2
valid_sources[0x44]	600030	1			T1	2		T17	3		T18	39
valid_sources[0x45]	283280	1			T1	6		T12	4		T17	1
valid_sources[0x46]	288122	1			T12	12		T17	3		T18	22
valid_sources[0x47]	300205	1			T4	4		T12	6		T18	49
valid_sources[0x48]	281170	1			T1	2		T4	5		T17	8
valid_sources[0x49]	281967	1			T1	3		T12	2		T17	4
valid_sources[0x4a]	281602	1			T1	3		T17	3		T18	37
valid_sources[0x4b]	282973	1			T1	6		T4	1		T17	2
valid_sources[0x4c]	438884	1			T1	1		T4	3		T17	2
valid_sources[0x4d]	372090	1			T1	2		T4	1		T18	26
valid_sources[0x4e]	285476	1			T1	2		T12	3		T18	27
valid_sources[0x4f]	296744	1			T1	4		T17	1		T18	41
valid_sources[0x50]	468438	1			T1	4		T4	1		T12	1
valid_sources[0x51]	1079273	1			T1	1		T4	1		T12	6
valid_sources[0x52]	466469	1			T1	1		T12	6		T18	33
valid_sources[0x53]	282068	1			T1	2		T12	10		T17	2
valid_sources[0x54]	283255	1			T1	2		T4	3		T12	5
valid_sources[0x55]	287960	1			T1	3		T4	1		T12	3
valid_sources[0x56]	362605	1			T1	3		T4	1		T18	51
valid_sources[0x57]	306009	1			T1	1		T4	1		T17	1
valid_sources[0x58]	449565	1			T1	2		T4	1		T12	8
valid_sources[0x59]	283536	1			T1	3		T4	2		T12	9
valid_sources[0x5a]	402945	1			T1	3		T4	2		T12	3
valid_sources[0x5b]	386452	1			T1	2		T12	7		T17	1
valid_sources[0x5c]	422018	1			T1	2		T18	28		T95	54
valid_sources[0x5d]	413380	1			T1	3		T12	2		T17	5
valid_sources[0x5e]	282842	1			T1	2		T4	1		T12	4
valid_sources[0x5f]	281450	1			T1	3		T4	1		T12	9
valid_sources[0x60]	413565	1			T4	2		T12	3		T18	34
valid_sources[0x61]	280733	1			T1	3		T4	1		T12	5
valid_sources[0x62]	302011	1			T1	3		T12	2		T17	2
valid_sources[0x63]	285875	1			T1	1		T4	1		T17	5
valid_sources[0x64]	364731	1			T1	5		T4	1		T12	4
valid_sources[0x65]	284947	1			T1	5		T17	1		T18	39
valid_sources[0x66]	339896	1			T1	3		T4	2		T18	36
valid_sources[0x67]	770478	1			T1	4		T4	1		T12	4
valid_sources[0x68]	283421	1			T1	3		T12	1		T17	4
valid_sources[0x69]	386790	1			T1	2		T4	1		T12	2
valid_sources[0x6a]	292672	1			T4	4		T12	4		T17	4
valid_sources[0x6b]	434485	1			T1	1		T4	1		T17	4
valid_sources[0x6c]	281958	1			T4	3		T18	40		T95	65
valid_sources[0x6d]	284401	1			T1	6		T18	49		T95	58
valid_sources[0x6e]	282456	1			T1	2		T12	2		T18	46
valid_sources[0x6f]	285046	1			T1	2		T4	1		T17	1
valid_sources[0x70]	283037	1			T1	2		T12	6		T17	10
valid_sources[0x71]	281945	1			T1	3		T4	1		T17	1
valid_sources[0x72]	278963	1			T1	2		T4	1		T17	1
valid_sources[0x73]	1278290	1			T1	1		T12	1		T17	2
valid_sources[0x74]	282893	1			T1	1		T4	1		T12	24
valid_sources[0x75]	416748	1			T1	4		T4	1		T17	3
valid_sources[0x76]	279143	1			T1	2		T4	1		T15	529
valid_sources[0x77]	1242511	1			T1	4		T4	7		T12	2
valid_sources[0x78]	284058	1			T1	3		T4	2		T12	3
valid_sources[0x79]	294173	1			T1	5		T4	3		T12	3
valid_sources[0x7a]	319556	1			T1	5		T18	29		T95	43
valid_sources[0x7b]	284453	1			T1	2		T4	1		T17	1
valid_sources[0x7c]	286262	1			T1	1		T4	1		T12	5
valid_sources[0x7d]	393766	1			T1	3		T4	4		T17	4
valid_sources[0x7e]	283737	1			T1	5		T4	1		T12	10
valid_sources[0x7f]	310602	1			T1	4		T4	2		T12	1
valid_sources[0x80]	477415	1			T1	6		T12	5		T17	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24166682

1

T1

224

T2

271

T3

87

values[0x0]

all_enables

biggest_size

13024767

1

T1

100

T2

139

T3

42

values[0x1]

all_enables

biggest_size

11722020

1

T1

114

T2

144

T3

44