Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

40110702

1

T1

237

T2

330

T3

18

full_word

48914677

1

T1

438

T2

554

T3

173

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	89025069	1			T1	675		T2	884		T3	191
auto[TlIntgErrCmd]	102	1			T61	3		T123	3		T127	7
auto[TlIntgErrData]	96	1			T61	3		T123	4		T127	5
auto[TlIntgErrBoth]	112	1			T61	4		T123	3		T127	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48780372

1

T1

347

T2

465

T3

90

auto[1]

40245007

1

T1

328

T2

419

T3

101

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24613230	1			T1	123		T2	194		T3	3
auto[TlIntgErrNone]	partial	auto[1]	15497189	1			T1	114		T2	136		T3	15
auto[TlIntgErrNone]	full_word	auto[0]	24167000	1			T1	224		T2	271		T3	87
auto[TlIntgErrNone]	full_word	auto[1]	24747650	1			T1	214		T2	283		T3	86
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T61	1		T123	1		T127	5
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T61	2		T127	1		T182	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T123	1		T184	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T123	1		T127	1		T184	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T61	3		T123	1		T127	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T123	3		T127	2		T184	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T186	1		T183	1		T187	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T127	1		T188	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T61	3		T127	2		T184	5
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T61	1		T123	2		T127	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T180	1		T181	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T123	1		T185	2		T189	1