Line Coverage for Module :
kmac_app
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 222 | 202 | 90.99 |
| ALWAYS | 290 | 6 | 5 | 83.33 |
| ALWAYS | 304 | 0 | 0 | |
| ALWAYS | 304 | 4 | 4 | 100.00 |
| ALWAYS | 329 | 6 | 6 | 100.00 |
| ALWAYS | 348 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 372 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 373 | 1 | 1 | 100.00 |
| ALWAYS | 376 | 3 | 3 | 100.00 |
| ALWAYS | 385 | 3 | 3 | 100.00 |
| ALWAYS | 388 | 1 | 0 | 0.00 |
| ALWAYS | 393 | 95 | 78 | 82.11 |
| CONT_ASSIGN | 653 | 1 | 1 | 100.00 |
| ALWAYS | 659 | 3 | 3 | 100.00 |
| ALWAYS | 682 | 18 | 18 | 100.00 |
| ALWAYS | 726 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 746 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 757 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 768 | 1 | 1 | 100.00 |
| ALWAYS | 790 | 13 | 13 | 100.00 |
| ALWAYS | 815 | 6 | 6 | 100.00 |
| ALWAYS | 843 | 3 | 3 | 100.00 |
| ALWAYS | 853 | 20 | 20 | 100.00 |
| ALWAYS | 904 | 8 | 7 | 87.50 |
| ALWAYS | 933 | 16 | 16 | 100.00 |
| ALWAYS | 960 | 3 | 3 | 100.00 |
289 always_ff @(posedge clk_i or negedge rst_ni) begin
290 2/2 if (!rst_ni) service_rejected_error <= 1'b 0;
Tests: T1 T2 T3 | T1 T2 T3
291 1/2 ==> else if (service_rejected_error_set) service_rejected_error <= 1'b 1;
Tests: T1 T2 T3
292 2/2 else if (service_rejected_error_clr) service_rejected_error <= 1'b 0;
Tests: T1 T2 T3 | T4 T17 T20
MISSING_ELSE
293 end
294
295 ////////////////////////////
296 // Application Mux/ Demux //
297 ////////////////////////////
298
299
300 // Processing return data.
301 // sends to only selected app intf.
302 // clear digest right after done to not leak info to other interface
303 always_comb begin
304 1/1 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin
Tests: T1 T2 T3
305 1/1 if (i == app_id) begin
Tests: T1 T2 T3
306 1/1 app_o[i] = '{
Tests: T1 T2 T3
307 ready: app_data_ready | fsm_data_ready,
308 done: app_digest_done | fsm_digest_done_q,
309 digest_share0: app_digest[0],
310 digest_share1: app_digest[1],
311 // if fsm asserts done, should be an error case.
312 error: error_i | fsm_digest_done_q | sparse_fsm_error_o
313 | service_rejected_error
314 };
315 end else begin
316 1/1 app_o[i] = '{
Tests: T1 T2 T3
317 ready: 1'b 0,
318 done: 1'b 0,
319 digest_share0: '0,
320 digest_share1: '0,
321 error: 1'b 0
322 };
323 end
324 end // for {i, NumAppIntf, i++}
325 end // aiways_comb
326
327 // app_id latch
328 always_ff @(posedge clk_i or negedge rst_ni) begin
329 2/2 if (!rst_ni) app_id <= AppIdxW'(0) ; // Do not select any
Tests: T1 T2 T3 | T1 T2 T3
330 2/2 else if (clr_appid) app_id <= AppIdxW'(0);
Tests: T1 T2 T3 | T4 T17 T21
331 2/2 else if (set_appid) app_id <= app_id_d;
Tests: T1 T2 T3 | T3 T4 T5
MISSING_ELSE
332 end
333
334 // app_id selection as of now, app_id uses Priority. The assumption is that
335 // the request normally does not collide. (ROM_CTRL activates very early
336 // stage at the boot sequence)
337 //
338 // If this assumption is not true, consider RR arbiter.
339
340 // Prep for arbiter
341 logic [NumAppIntf-1:0] app_reqs;
342 logic [NumAppIntf-1:0] unused_app_gnts;
343 logic [$clog2(NumAppIntf)-1:0] arb_idx;
344 logic arb_valid;
345 logic arb_ready;
346
347 always_comb begin
348 1/1 app_reqs = '0;
Tests: T3 T4 T5
349 1/1 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin
Tests: T3 T4 T5
350 1/1 app_reqs[i] = app_i[i].valid;
Tests: T3 T4 T5
351 end
352 end
353
354 prim_arbiter_fixed #(
355 .N (NumAppIntf),
356 .DW(1),
357 .EnDataPort(1'b 0)
358 ) u_appid_arb (
359 .clk_i,
360 .rst_ni,
361
362 .req_i (app_reqs),
363 .data_i ('{default:'0}),
364 .gnt_o (unused_app_gnts),
365 .idx_o (arb_idx),
366
367 .valid_o (arb_valid),
368 .data_o (), // not used
369 .ready_i (arb_ready)
370 );
371
372 1/1 assign app_id_d = AppIdxW'(arb_idx);
Tests: T3 T21 T22
373 1/1 assign arb_ready = set_appid;
Tests: T3 T4 T5
374
375 always_ff @(posedge clk_i or negedge rst_ni) begin
376 2/2 if (!rst_ni) fsm_digest_done_q <= 1'b 0;
Tests: T1 T2 T3 | T1 T2 T3
377 1/1 else fsm_digest_done_q <= fsm_digest_done_d;
Tests: T1 T2 T3
378 end
379
380 /////////
381 // FSM //
382 /////////
383
384 // State register
385 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, st_e, StIdle)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, st_e, StIdle):
385.1 `ifdef SIMULATION
385.2 prim_sparse_fsm_flop #(
385.3 .StateEnumT(st_e),
385.4 .Width($bits(st_e)),
385.5 .ResetValue($bits(st_e)'(StIdle)),
385.6 .EnableAlertTriggerSVA(1),
385.7 .CustomForceName("st")
385.8 ) u_state_regs (
385.9 .clk_i ( clk_i ),
385.10 .rst_ni ( rst_ni ),
385.11 .state_i ( st_d ),
385.12 .state_o ( )
385.13 );
385.14 always_ff @(posedge clk_i or negedge rst_ni) begin
385.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
385.16 1/1 st <= StIdle;
Tests: T1 T2 T3
385.17 end else begin
385.18 1/1 st <= st_d;
Tests: T1 T2 T3
385.19 end
385.20 end
385.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (st === u_state_regs.state_o))
385.22 else begin
385.23 `ifdef UVM
385.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
385.25 "../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv", 385, "", 1);
385.26 `else
385.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
385.28 `PRIM_STRINGIFY(u_state_regs_A));
385.29 `endif
385.30 end
385.31 `else
385.32 prim_sparse_fsm_flop #(
385.33 .StateEnumT(st_e),
385.34 .Width($bits(st_e)),
385.35 .ResetValue($bits(st_e)'(StIdle)),
385.36 .EnableAlertTriggerSVA(1)
385.37 ) u_state_regs (
385.38 .clk_i ( `PRIM_FLOP_CLK ),
385.39 .rst_ni ( `PRIM_FLOP_RST ),
385.40 .state_i ( st_d ),
385.41 .state_o ( st )
385.42 );
385.43 `endif386
387 // Create a lint error to reduce the risk of accidentally enabling this feature.
388 0/1 ==> `ASSERT_STATIC_LINT_ERROR(KmacSecIdleAcceptSwMsgNonDefault, SecIdleAcceptSwMsg == 0)
ASSERT_STATIC_LINT_ERROR(KmacSecIdleAcceptSwMsgNonDefault, SecIdleAcceptSwMsg == 0):
388.1 localparam int KmacSecIdleAcceptSwMsgNonDefault = (SecIdleAcceptSwMsg == 0) ? 1 : 2;
388.2 always_comb begin
388.3 logic unused_assert_static_lint_error;
388.4 0/1 ==> unused_assert_static_lint_error = KmacSecIdleAcceptSwMsgNonDefault'(1'b1);
388.5 end389
390 // Next State & output logic
391 // SEC_CM: FSM.SPARSE
392 always_comb begin
393 1/1 st_d = st;
Tests: T1 T2 T3
394
395 1/1 mux_sel = SecIdleAcceptSwMsg ? SelSw : SelNone;
Tests: T1 T2 T3
396
397 // app_id control
398 1/1 set_appid = 1'b 0;
Tests: T1 T2 T3
399 1/1 clr_appid = 1'b 0;
Tests: T1 T2 T3
400
401 // Commands
402 1/1 cmd_o = CmdNone;
Tests: T1 T2 T3
403
404 // Software output
405 1/1 absorbed_o = prim_mubi_pkg::MuBi4False;
Tests: T1 T2 T3
406
407 // Error
408 1/1 fsm_err = '{valid: 1'b 0, code: ErrNone, info: '0};
Tests: T1 T2 T3
409 1/1 sparse_fsm_error_o = 1'b 0;
Tests: T1 T2 T3
410
411 1/1 clear_after_error_o = prim_mubi_pkg::MuBi4False;
Tests: T1 T2 T3
412
413 1/1 service_rejected_error_set = 1'b 0;
Tests: T1 T2 T3
414 1/1 service_rejected_error_clr = 1'b 0;
Tests: T1 T2 T3
415
416 // If error happens, FSM asserts data ready but discard incoming msg
417 1/1 fsm_data_ready = 1'b 0;
Tests: T1 T2 T3
418 1/1 fsm_digest_done_d = 1'b 0;
Tests: T1 T2 T3
419
420 1/1 unique case (st)
Tests: T1 T2 T3
421 StIdle: begin
422 1/1 if (arb_valid) begin
Tests: T1 T2 T3
423 1/1 st_d = StAppCfg;
Tests: T3 T4 T5
424
425 // choose app_id
426 1/1 set_appid = 1'b 1;
Tests: T3 T4 T5
427 1/1 end else if (sw_cmd_i == CmdStart) begin
Tests: T1 T2 T3
428 1/1 st_d = StSw;
Tests: T1 T2 T12
429 // Software initiates the sequence
430 1/1 cmd_o = CmdStart;
Tests: T1 T2 T12
431 end else begin
432 1/1 st_d = StIdle;
Tests: T1 T2 T3
433 end
434 end
435
436 StAppCfg: begin
437 1/1 if (AppCfg[app_id].Mode == AppKMAC &&
Tests: T3 T4 T5
438 prim_mubi_pkg::mubi4_test_false_strict(entropy_ready_i)) begin
439 // Check if the entropy is not configured but it is needed in
440 // `AppCfg[app_id]` (KMAC mode).
441 //
442 // SW is not properly configured, report and not request Hashing
443 // Return the app with errors
444 0/1 ==> st_d = StError;
445
446 0/1 ==> service_rejected_error_set = 1'b 1;
447
448 end else begin
449 // As Cfg is stable now, it sends cmd
450 1/1 st_d = StAppMsg;
Tests: T3 T4 T5
451
452 // App initiates the data
453 1/1 cmd_o = CmdStart;
Tests: T3 T4 T5
454 end
455 end
456
457 StAppMsg: begin
458 1/1 mux_sel = SelApp;
Tests: T3 T5 T21
459 1/1 if (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last) begin
Tests: T3 T5 T21
460 1/1 if (AppCfg[app_id].Mode == AppKMAC) begin
Tests: T21 T22 T23
461 1/1 st_d = StAppOutLen;
Tests: T21 T24 T25
462 end else begin
463 1/1 st_d = StAppProcess;
Tests: T21 T22 T23
464 end
465 end else begin
466 1/1 st_d = StAppMsg;
Tests: T3 T5 T21
467 end
468 end
469
470 StAppOutLen: begin
471 1/1 mux_sel = SelOutLen;
Tests: T21 T24 T25
472
473 1/1 if (kmac_valid_o && kmac_ready_i) begin
Tests: T21 T24 T25
474 1/1 st_d = StAppProcess;
Tests: T21 T24 T25
475 end else begin
476 1/1 st_d = StAppOutLen;
Tests: T24 T26 T27
477 end
478 end
479
480 StAppProcess: begin
481 1/1 cmd_o = CmdProcess;
Tests: T21 T22 T23
482 1/1 st_d = StAppWait;
Tests: T21 T22 T23
483 end
484
485 StAppWait: begin
486 1/1 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin
Tests: T21 T22 T23
487 // Send digest to KeyMgr and complete the op
488 1/1 st_d = StIdle;
Tests: T21 T22 T23
489 1/1 cmd_o = CmdDone;
Tests: T21 T22 T23
490
491 1/1 clr_appid = 1'b 1;
Tests: T21 T22 T23
492 end else begin
493 1/1 st_d = StAppWait;
Tests: T21 T22 T23
494 end
495 end
496
497 StSw: begin
498 1/1 mux_sel = SelSw;
Tests: T1 T2 T12
499
500 1/1 cmd_o = sw_cmd_i;
Tests: T1 T2 T12
501 1/1 absorbed_o = absorbed_i;
Tests: T1 T2 T12
502
503 1/1 if (sw_cmd_i == CmdDone) begin
Tests: T1 T2 T12
504 1/1 st_d = StIdle;
Tests: T1 T2 T12
505 end else begin
506 1/1 st_d = StSw;
Tests: T1 T2 T12
507 end
508 end
509
510 StKeyMgrErrKeyNotValid: begin
511 1/1 st_d = StError;
Tests: T4 T17 T20
512
513 // As mux_sel is not set to SelApp, app_data_ready is still 0.
514 // This logic won't accept the requests from the selected App.
515 1/1 fsm_err.valid = 1'b 1;
Tests: T4 T17 T20
516 1/1 fsm_err.code = ErrKeyNotValid;
Tests: T4 T17 T20
517 1/1 fsm_err.info = 24'(app_id);
Tests: T4 T17 T20
518 end
519
520 StError: begin
521 // In this state, the state machine flush out the request
522 1/1 st_d = StError;
Tests: T4 T17 T20
523
524 // Absorb data on the app interface.
525 1/1 fsm_data_ready = ~err_during_sw_q;
Tests: T4 T17 T20
526
527 // Next step depends on two conditions:
528 // 1) Error being processed by SW
529 // 2) Last data provided from the app interface (so that the app interface is completely)
530 // drained. If the error occurred during a SW operation, the app interface is not
531 // involved, so this condition gets skipped.
532 1/1 unique case ({err_processed_i,
Tests: T4 T17 T20
533 (app_i[app_id].valid && app_i[app_id].last) || err_during_sw_q})
534 2'b00: begin
535 // Error not processed by SW and not last data from app interface -> keep current state.
536 1/1 st_d = StError;
Tests: T4 T17 T20
537 end
538 2'b01: begin
539 // Error not processed by SW but last data from app interface:
540 // 1. Send garbage digest to the app interface (in the next cycle) to complete the
541 // transaction.
542 1/1 fsm_digest_done_d = ~err_during_sw_q;
Tests: T4 T17 T20
543 1/1 if (service_rejected_error) begin
Tests: T4 T17 T20
544 // 2.a) Service was rejected because an app interface tried to configure KMAC while no
545 // entropy was available. It is assumed that SW is not loaded yet, so don't wait for
546 // SW to process the error. The last data from the app interface has now arrived, but
547 // we don't need to wait for the SHA3 core to have absorbed it because the data never
548 // entered the SHA3 core: the request from the app interface was terminated during the
549 // configuration phase.
550 0/1 ==> st_d = StErrorServiceRejected;
551 end else begin
552 // 2.b) If service was not rejected, wait for SW to process the error.
553 1/1 st_d = StErrorAwaitSw;
Tests: T4 T17 T20
554 end
555 end
556 2'b10: begin
557 // Error processed by SW but not last data from app interface -> wait for app interface.
558 0/1 ==> st_d = StErrorAwaitApp;
559 end
560 2'b11: begin
561 // Error processed by SW and last data from app interface:
562 // Send garbage digest to the app interface (in the next cycle) to complete the
563 // transaction.
564 0/1 ==> fsm_digest_done_d = ~err_during_sw_q;
565 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
566 // but serves to bring the SHA3 engine back to the idle state).
567 0/1 ==> cmd_o = CmdProcess;
568 0/1 ==> st_d = StErrorWaitAbsorbed;
569 end
570 default: st_d = StError;
571 endcase
572 end
573
574 StErrorAwaitSw: begin
575 // Just wait for SW to process the error.
576 1/1 if (err_processed_i) begin
Tests: T4 T17 T20
577 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
578 // but serves to bring the SHA3 engine back to the idle state).
579 1/1 cmd_o = CmdProcess;
Tests: T4 T17 T20
580 1/1 st_d = StErrorWaitAbsorbed;
Tests: T4 T17 T20
581 end
MISSING_ELSE
582 end
583
584 StErrorAwaitApp: begin
585 // Keep absorbing data on the app interface until the last data.
586 0/1 ==> fsm_data_ready = 1'b1;
587 0/1 ==> if (app_i[app_id].valid && app_i[app_id].last) begin
588 // Send garbage digest to the app interface (in the next cycle) to complete the
589 // transaction.
590 0/1 ==> fsm_digest_done_d = 1'b1;
591 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
592 // but serves to bring the SHA3 engine back to the idle state).
593 0/1 ==> cmd_o = CmdProcess;
594 0/1 ==> st_d = StErrorWaitAbsorbed;
595 end
==> MISSING_ELSE
596 end
597
598 StErrorWaitAbsorbed: begin
599 1/1 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin
Tests: T4 T17 T20
600 // Clear internal variables, send done command, and return to idle.
601 1/1 clr_appid = 1'b1;
Tests: T4 T17 T20
602 1/1 clear_after_error_o = prim_mubi_pkg::MuBi4True;
Tests: T4 T17 T20
603 1/1 service_rejected_error_clr = 1'b1;
Tests: T4 T17 T20
604 1/1 cmd_o = CmdDone;
Tests: T4 T17 T20
605 1/1 st_d = StIdle;
Tests: T4 T17 T20
606 // If error originated from SW, report 'absorbed' to SW.
607 1/1 if (err_during_sw_q) begin
Tests: T4 T17 T20
608 0/1 ==> absorbed_o = prim_mubi_pkg::MuBi4True;
609 end
MISSING_ELSE
610 end
MISSING_ELSE
611 end
612
613 StErrorServiceRejected: begin
614 // Clear internal variables and return to idle.
615 0/1 ==> clr_appid = 1'b1;
616 0/1 ==> clear_after_error_o = prim_mubi_pkg::MuBi4True;
617 0/1 ==> service_rejected_error_clr = 1'b1;
618 0/1 ==> st_d = StIdle;
619 end
620
621 StTerminalError: begin
622 // this state is terminal
623 1/1 st_d = st;
Tests: T3 T5 T6
624 1/1 sparse_fsm_error_o = 1'b 1;
Tests: T3 T5 T6
625 1/1 fsm_err.valid = 1'b 1;
Tests: T3 T5 T6
626 1/1 fsm_err.code = ErrFatalError;
Tests: T3 T5 T6
627 1/1 fsm_err.info = 24'(app_id);
Tests: T3 T5 T6
628 end
629
630 default: begin
631 st_d = StTerminalError;
632 sparse_fsm_error_o = 1'b 1;
633 end
634 endcase
635
636 // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC
637 // Unconditionally jump into the terminal error state
638 // if the life cycle controller triggers an escalation.
639 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
Tests: T1 T2 T3
640 1/1 st_d = StTerminalError;
Tests: T3 T5 T6
641 end
MISSING_ELSE
642
643 // Handle errors outside the terminal error state.
644 1/1 if (st_d != StTerminalError) begin
Tests: T1 T2 T3
645 // Key from keymgr is used but not valid, so abort into the invalid key error state.
646 1/1 if (keymgr_key_used && !keymgr_key_i.valid) begin
Tests: T1 T2 T3
647 1/1 st_d = StKeyMgrErrKeyNotValid;
Tests: T4 T17 T20
648 end
MISSING_ELSE
649 end
MISSING_ELSE
650 end
651
652 // Track errors occurring in SW mode.
653 1/1 assign err_during_sw_d =
Tests: T1 T2 T3
654 (mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}) ? 1'b1 : // set
655 (st_d == StIdle) ? 1'b0 : // clear
656 err_during_sw_q; // hold
657
658 always_ff @(posedge clk_i or negedge rst_ni) begin
659 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
660 1/1 err_during_sw_q <= 1'b0;
Tests: T1 T2 T3
661 end else begin
662 1/1 err_during_sw_q <= err_during_sw_d;
Tests: T1 T2 T3
663 end
664 end
665
666 //////////////
667 // Datapath //
668 //////////////
669
670 // Encoded output length
671 assign encoded_outlen = EncodedOutLen[SelDigSize];
672 assign encoded_outlen_mask = EncodedOutLenMask[SelKeySize];
673
674 // Data mux
675 // This is the main part of the KeyMgr interface logic.
676 // The FSM selects KeyMgr interface in a cycle after it receives the first
677 // valid data from KeyMgr. The ready signal to the KeyMgr data interface
678 // represents the MSG_FIFO ready, only when it is in StKeyMgrMsg state.
679 // After KeyMgr sends last beat, the kmac interface (to MSG_FIFO) is switched
680 // to OutLen. OutLen is pre-defined values. See `EncodeOutLen` parameter above.
681 always_comb begin
682 1/1 app_data_ready = 1'b 0;
Tests: T1 T2 T3
683 1/1 sw_ready_o = 1'b 1;
Tests: T1 T2 T3
684
685 1/1 kmac_valid_o = 1'b 0;
Tests: T1 T2 T3
686 1/1 kmac_data_o = '0;
Tests: T1 T2 T3
687 1/1 kmac_mask_o = '0;
Tests: T1 T2 T3
688
689 1/1 unique case (mux_sel_buf_kmac)
Tests: T1 T2 T3
690 SelApp: begin
691 // app_id is valid at this time
692 1/1 kmac_valid_o = app_i[app_id].valid;
Tests: T3 T5 T21
693 1/1 kmac_data_o = app_i[app_id].data;
Tests: T3 T5 T21
694 // Expand strb to bits. prim_packer inside MSG_FIFO accepts the bit masks
695 1/1 for (int i = 0 ; i < $bits(app_i[app_id].strb) ; i++) begin
Tests: T3 T5 T21
696 1/1 kmac_mask_o[8*i+:8] = {8{app_i[app_id].strb[i]}};
Tests: T3 T5 T21
697 end
698 1/1 app_data_ready = kmac_ready_i;
Tests: T3 T5 T21
699 end
700
701 SelOutLen: begin
702 // Write encoded output length value
703 1/1 kmac_valid_o = 1'b 1; // always write
Tests: T21 T24 T25
704 1/1 kmac_data_o = MsgWidth'(encoded_outlen);
Tests: T21 T24 T25
705 1/1 kmac_mask_o = MsgWidth'(encoded_outlen_mask);
Tests: T21 T24 T25
706 end
707
708 SelSw: begin
709 1/1 kmac_valid_o = sw_valid_i;
Tests: T1 T2 T12
710 1/1 kmac_data_o = sw_data_i ;
Tests: T1 T2 T12
711 1/1 kmac_mask_o = sw_mask_i ;
Tests: T1 T2 T12
712 1/1 sw_ready_o = kmac_ready_i ;
Tests: T1 T2 T12
713 end
714
715 default: begin // Incl. SelNone
716 kmac_valid_o = 1'b 0;
717 kmac_data_o = '0;
718 kmac_mask_o = '0;
719 end
720
721 endcase
722 end
723
724 // Error checking for Mux
725 always_comb begin
726 1/1 mux_err = '{valid: 1'b 0, code: ErrNone, info: '0};
Tests: T1 T2 T3
727
728 1/1 if (mux_sel_buf_err_check != SelSw && sw_valid_i) begin
Tests: T1 T2 T3
729 // If SW writes message into FIFO
730 1/1 mux_err = '{
Tests: T3 T5 T6
731 valid: 1'b 1,
732 code: ErrSwPushedMsgFifo,
733 info: 24'({8'h 00, 8'(st), 8'(mux_sel_buf_err_check)})
734 };
735 1/1 end else if (app_active_o && sw_cmd_i != CmdNone) begin
Tests: T1 T2 T3
736 // If SW issues command except start
737 1/1 mux_err = '{
Tests: T28 T29 T30
738 valid: 1'b 1,
739 code: ErrSwIssuedCmdInAppActive,
740 info: 24'(sw_cmd_i)
741 };
742 end
MISSING_ELSE
743 end
744
745 logic [AppMuxWidth-1:0] mux_sel_buf_output_logic;
746 1/1 assign mux_sel_buf_output = app_mux_sel_e'(mux_sel_buf_output_logic);
Tests: T1 T2 T3
747
748 // SEC_CM: LOGIC.INTEGRITY
749 prim_sec_anchor_buf #(
750 .Width(AppMuxWidth)
751 ) u_prim_buf_state_output_sel (
752 .in_i(mux_sel),
753 .out_o(mux_sel_buf_output_logic)
754 );
755
756 logic [AppMuxWidth-1:0] mux_sel_buf_err_check_logic;
757 1/1 assign mux_sel_buf_err_check = app_mux_sel_e'(mux_sel_buf_err_check_logic);
Tests: T1 T2 T3
758
759 // SEC_CM: LOGIC.INTEGRITY
760 prim_sec_anchor_buf #(
761 .Width(AppMuxWidth)
762 ) u_prim_buf_state_err_check (
763 .in_i(mux_sel),
764 .out_o(mux_sel_buf_err_check_logic)
765 );
766
767 logic [AppMuxWidth-1:0] mux_sel_buf_kmac_logic;
768 1/1 assign mux_sel_buf_kmac = app_mux_sel_e'(mux_sel_buf_kmac_logic);
Tests: T1 T2 T3
769
770 // SEC_CM: LOGIC.INTEGRITY
771 prim_sec_anchor_buf #(
772 .Width(AppMuxWidth)
773 ) u_prim_buf_state_kmac_sel (
774 .in_i(mux_sel),
775 .out_o(mux_sel_buf_kmac_logic)
776 );
777
778 // SEC_CM: LOGIC.INTEGRITY
779 logic reg_state_valid;
780 prim_sec_anchor_buf #(
781 .Width(1)
782 ) u_prim_buf_state_output_valid (
783 .in_i(reg_state_valid),
784 .out_o(reg_state_valid_o)
785 );
786
787 // Keccak state Demux
788 // Keccak state --> Register output is enabled when state is in StSw
789 always_comb begin
790 1/1 reg_state_valid = 1'b 0;
Tests: T1 T2 T3
791 1/1 reg_state_o = '{default:'0};
Tests: T1 T2 T3
792 1/1 if ((mux_sel_buf_output == SelSw) &&
Tests: T1 T2 T3
793 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin
794 1/1 reg_state_valid = keccak_state_valid_i;
Tests: T1 T2 T12
795 1/1 reg_state_o = keccak_state_i;
Tests: T1 T2 T12
796 // If key is sideloaded and KMAC is SW initiated
797 // hide the capacity from SW by zeroing (see #17508)
798 1/1 if (keymgr_key_en_i) begin
Tests: T1 T2 T12
799 1/1 for (int i = 0; i < Share; i++) begin
Tests: T31 T32 T22
800 1/1 unique case (reg_keccak_strength_i)
Tests: T31 T32 T22
801 1/1 L128: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L128]] = '0;
Tests: T31 T32 T22
802 1/1 L224: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L224]] = '0;
Tests: T27 T33 T34
803 1/1 L256: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L256]] = '0;
Tests: T31 T22 T25
804 1/1 L384: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L384]] = '0;
Tests: T35 T34 T36
805 1/1 L512: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L512]] = '0;
Tests: T37 T38 T39
806 default: reg_state_o[i] = '0;
807 endcase
808 end
809 end
MISSING_ELSE
810 end
MISSING_ELSE
811 end
812
813 // Keccak state --> KeyMgr
814 always_comb begin
815 1/1 app_digest_done = 1'b 0;
Tests: T1 T2 T3
816 1/1 app_digest = '{default:'0};
Tests: T1 T2 T3
817 1/1 if (st == StAppWait && prim_mubi_pkg::mubi4_test_true_strict(absorbed_i) &&
Tests: T1 T2 T3
818 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin
819 // SHA3 engine has calculated the hash. Return the data to KeyMgr
820 1/1 app_digest_done = 1'b 1;
Tests: T21 T22 T23
821
822 // digest has always 2 entries. If !EnMasking, second is tied to 0.
823 1/1 for (int i = 0 ; i < Share ; i++) begin
Tests: T21 T22 T23
824 // Return the portion of state.
825 1/1 app_digest[i] = keccak_state_i[i][AppDigestW-1:0];
Tests: T21 T22 T23
826 end
827 end
MISSING_ELSE
828 end
829
830
831 // Secret Key Mux
832
833 // Prepare merged key if EnMasking is not set.
834 // Combine share keys into unpacked array for logic below to assign easily.
835 // SEC_CM: KEY.SIDELOAD
836 logic [MaxKeyLen-1:0] keymgr_key [Share];
837 if (EnMasking == 1) begin : g_masked_key
838 for (genvar i = 0; i < Share; i++) begin : gen_key_pad
839 assign keymgr_key[i] = {(MaxKeyLen-KeyMgrKeyW)'(0), keymgr_key_i.key[i]};
840 end
841 end else begin : g_unmasked_key
842 always_comb begin
843 1/1 keymgr_key[0] = '0;
Tests: T5 T31 T40
844 1/1 for (int i = 0; i < keymgr_pkg::Shares; i++) begin
Tests: T5 T31 T40
845 1/1 keymgr_key[0][KeyMgrKeyW-1:0] ^= keymgr_key_i.key[i];
Tests: T5 T31 T40
846 end
847 end
848 end
849
850 // Sideloaded key manage: Keep use sideloaded key for KMAC AppIntf until the
851 // hashing operation is finished.
852 always_comb begin
853 1/1 keymgr_key_used = 1'b0;
Tests: T1 T2 T3
854 1/1 key_len_o = reg_key_len_i;
Tests: T1 T2 T3
855 1/1 for (int i = 0 ; i < Share; i++) begin
Tests: T1 T2 T3
856 1/1 key_data_o[i] = reg_key_data_i[i];
Tests: T1 T2 T3
857 end
858 // The key is considered invalid in all cases that are not listed below (which includes idle and
859 // error states).
860 1/1 key_valid_o = 1'b0;
Tests: T1 T2 T3
861
862 1/1 unique case (st)
Tests: T1 T2 T3
863 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin
864 // Key from keymgr is actually used if the current HW app interface does *keyed* MAC.
865 1/1 keymgr_key_used = AppCfg[app_id].Mode == AppKMAC;
Tests: T3 T4 T5
866 1/1 key_len_o = SideloadedKey;
Tests: T3 T4 T5
867 1/1 for (int i = 0 ; i < Share; i++) begin
Tests: T3 T4 T5
868 1/1 key_data_o[i] = keymgr_key[i];
Tests: T3 T4 T5
869 end
870 // Key is valid if the current HW app interface does *keyed* MAC and the key provided by
871 // keymgr is valid.
872 1/1 key_valid_o = keymgr_key_used && keymgr_key_i.valid;
Tests: T3 T4 T5
873 end
874
875 StSw: begin
876 1/1 if (keymgr_key_en_i) begin
Tests: T1 T2 T12
877 // Key from keymgr is actually used if *keyed* MAC is enabled.
878 1/1 keymgr_key_used = kmac_en_o;
Tests: T31 T32 T22
879 1/1 key_len_o = SideloadedKey;
Tests: T31 T32 T22
880 1/1 for (int i = 0 ; i < Share; i++) begin
Tests: T31 T32 T22
881 1/1 key_data_o[i] = keymgr_key[i];
Tests: T31 T32 T22
882 end
883 end
MISSING_ELSE
884 // Key is valid if SW does *keyed* MAC and ...
885 1/1 if (kmac_en_o) begin
Tests: T1 T2 T12
886 1/1 if (!keymgr_key_en_i) begin
Tests: T1 T2 T12
887 // ... it uses the key from kmac's CSR, or ...
888 1/1 key_valid_o = 1'b1;
Tests: T1 T2 T12
889 end else begin
890 // ... it uses the key provided by keymgr and that one is valid.
891 1/1 key_valid_o = keymgr_key_i.valid;
Tests: T22 T25 T26
892 end
893 end
MISSING_ELSE
894 end
895
896 default: ;
897 endcase
898 end
899
900 // Prefix Demux
901 // For SW, always prefix register.
902 // For App intf, check PrefixMode cfg and if 1, use Prefix cfg.
903 always_comb begin
904 1/1 sha3_prefix_o = '0;
Tests: T1 T2 T3
905
906 1/1 unique case (st)
Tests: T1 T2 T3
907 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin
908 // Check app intf cfg
909 1/1 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin
Tests: T3 T4 T5
910 1/1 if (app_id == i) begin
Tests: T3 T4 T5
911 1/1 if (AppCfg[i].PrefixMode == 1'b 0) begin
Tests: T3 T4 T5
912 0/1 ==> sha3_prefix_o = reg_prefix_i;
913 end else begin
914 1/1 sha3_prefix_o = AppCfg[i].Prefix;
Tests: T3 T4 T5
915 end
916 end
MISSING_ELSE
917 end
918 end
919
920 StSw: begin
921 1/1 sha3_prefix_o = reg_prefix_i;
Tests: T1 T2 T12
922 end
923
924 default: begin
925 sha3_prefix_o = reg_prefix_i;
926 end
927 endcase
928 end
929
930 // KMAC en / SHA3 mode / Strength
931 // by default, it uses reg cfg. When app intf reqs come, it uses AppCfg.
932 always_ff @(posedge clk_i or negedge rst_ni) begin
933 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
934 1/1 kmac_en_o <= 1'b 0;
Tests: T1 T2 T3
935 1/1 sha3_mode_o <= sha3_pkg::Sha3;
Tests: T1 T2 T3
936 1/1 keccak_strength_o <= sha3_pkg::L256;
Tests: T1 T2 T3
937 1/1 end else if (clr_appid) begin
Tests: T1 T2 T3
938 // As App completed, latch reg value
939 1/1 kmac_en_o <= reg_kmac_en_i;
Tests: T4 T17 T21
940 1/1 sha3_mode_o <= reg_sha3_mode_i;
Tests: T4 T17 T21
941 1/1 keccak_strength_o <= reg_keccak_strength_i;
Tests: T4 T17 T21
942 1/1 end else if (set_appid) begin
Tests: T1 T2 T3
943 1/1 kmac_en_o <= AppCfg[arb_idx].Mode == AppKMAC ? 1'b 1 : 1'b 0;
Tests: T3 T4 T5
944 1/1 sha3_mode_o <= AppCfg[arb_idx].Mode == AppSHA3
Tests: T3 T4 T5
945 ? sha3_pkg::Sha3 : sha3_pkg::CShake;
946 1/1 keccak_strength_o <= AppCfg[arb_idx].Strength ;
Tests: T3 T4 T5
947 1/1 end else if (st == StIdle) begin
Tests: T1 T2 T3
948 1/1 kmac_en_o <= reg_kmac_en_i;
Tests: T1 T2 T3
949 1/1 sha3_mode_o <= reg_sha3_mode_i;
Tests: T1 T2 T3
950 1/1 keccak_strength_o <= reg_keccak_strength_i;
Tests: T1 T2 T3
951 end
MISSING_ELSE
952 end
953
954 // Status
955 assign app_active_o = (st inside {StAppCfg, StAppMsg, StAppOutLen,
956 StAppProcess, StAppWait});
957
958 // Error Reporting ==========================================================
959 always_comb begin
960 1/1 priority casez ({fsm_err.valid, mux_err.valid})
Tests: T1 T2 T3
961 1/1 2'b ?1: error_o = mux_err;
Tests: T3 T5 T6
962 1/1 2'b 10: error_o = fsm_err;
Tests: T3 T4 T5
963 default: error_o = '{valid: 1'b0, code: ErrNone, info: '0};
Cond Coverage for Module :
kmac_app
| Total | Covered | Percent |
|---|
| Conditions | 73 | 62 | 84.93 |
| Logical | 73 | 62 | 84.93 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 305
EXPRESSION (i == app_id)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 306
EXPRESSION (app_data_ready | fsm_data_ready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T17,T20 |
| 1 | 0 | Covered | T3,T5,T21 |
LINE 306
EXPRESSION (app_digest_done | fsm_digest_done_q)
-------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T17,T20 |
| 1 | 0 | Covered | T21,T22,T23 |
LINE 306
EXPRESSION (error_i | fsm_digest_done_q | sparse_fsm_error_o | service_rejected_error)
---1--- --------2-------- ---------3-------- -----------4----------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Not Covered | |
| 0 | 0 | 1 | 0 | Covered | T3,T5,T6 |
| 0 | 1 | 0 | 0 | Covered | T4,T17,T20 |
| 1 | 0 | 0 | 0 | Covered | T23,T41,T42 |
LINE 427
EXPRESSION (sw_cmd_i == CmdStart)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T12 |
LINE 459
EXPRESSION (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last)
---------1--------- ---------2--------- ---------3--------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T24,T26,T43 |
| 1 | 1 | 0 | Covered | T3,T5,T21 |
| 1 | 1 | 1 | Covered | T21,T22,T23 |
LINE 460
EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T21,T22,T23 |
| 1 | Covered | T21,T24,T25 |
LINE 473
EXPRESSION (kmac_valid_o && kmac_ready_i)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Unreachable | T24,T26,T27 |
| 1 | 1 | Covered | T21,T24,T25 |
LINE 503
EXPRESSION (sw_cmd_i == CmdDone)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T12 |
| 1 | Covered | T1,T2,T12 |
LINE 587
EXPRESSION (app_i[app_id].valid && app_i[app_id].last)
---------1--------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 644
EXPRESSION (st_d != StTerminalError)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T5,T6 |
| 1 | Covered | T1,T2,T3 |
LINE 646
EXPRESSION (keymgr_key_used && ((!keymgr_key_i.valid)))
-------1------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T21,T22 |
| 1 | 1 | Covered | T4,T17,T20 |
LINE 653
EXPRESSION (((mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid})) ? 1'b1 : ((st_d == StIdle) ? 1'b0 : err_during_sw_q))
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 653
SUB-EXPRESSION ((mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}))
---------1-------- -----------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T17,T20 |
| 1 | 0 | Covered | T1,T2,T12 |
| 1 | 1 | Not Covered | |
LINE 653
SUB-EXPRESSION (mux_sel == SelSw)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T12 |
LINE 653
SUB-EXPRESSION ((st_d == StIdle) ? 1'b0 : err_during_sw_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 653
SUB-EXPRESSION (st_d == StIdle)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 728
EXPRESSION ((mux_sel_buf_err_check != SelSw) && sw_valid_i)
----------------1--------------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T5,T6 |
LINE 728
SUB-EXPRESSION (mux_sel_buf_err_check != SelSw)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T12 |
| 1 | Covered | T1,T2,T3 |
LINE 735
EXPRESSION (app_active_o && (sw_cmd_i != CmdNone))
------1----- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T5 |
| 1 | 1 | Covered | T28,T29,T30 |
LINE 735
SUB-EXPRESSION (sw_cmd_i != CmdNone)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 865
EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T21,T22 |
| 1 | Covered | T4,T5,T17 |
LINE 872
EXPRESSION (keymgr_key_used && keymgr_key_i.valid)
-------1------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T44,T30,T45 |
| 1 | 0 | Covered | T4,T17,T20 |
| 1 | 1 | Covered | T5,T21,T24 |
LINE 910
EXPRESSION (app_id == i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Covered | T3,T4,T5 |
LINE 911
EXPRESSION (kmac_pkg::AppCfg[i].PrefixMode == 1'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Not Covered | |
LINE 943
EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC) ? 1'b1 : 1'b0)
---------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T21,T22 |
| 1 | Covered | T4,T5,T17 |
LINE 943
SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC)
---------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T21,T22 |
| 1 | Covered | T4,T5,T17 |
LINE 944
EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3) ? Sha3 : CShake)
---------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Not Covered | |
LINE 944
SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3)
---------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Not Covered | |
LINE 947
EXPRESSION (st == StIdle)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Module :
kmac_app
Summary for FSM :: st
| Total | Covered | Percent | |
| States |
14 |
12 |
85.71 |
(Not included in score) |
| Transitions |
45 |
18 |
40.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st
| states | Line No. | Covered | Tests |
| StAppCfg |
423 |
Covered |
T3,T4,T5 |
| StAppMsg |
450 |
Covered |
T3,T5,T21 |
| StAppOutLen |
461 |
Covered |
T21,T24,T25 |
| StAppProcess |
463 |
Covered |
T21,T22,T23 |
| StAppWait |
482 |
Covered |
T21,T22,T23 |
| StError |
444 |
Covered |
T4,T17,T20 |
| StErrorAwaitApp |
558 |
Not Covered |
|
| StErrorAwaitSw |
553 |
Covered |
T4,T17,T20 |
| StErrorServiceRejected |
550 |
Not Covered |
|
| StErrorWaitAbsorbed |
568 |
Covered |
T4,T17,T20 |
| StIdle |
432 |
Covered |
T1,T2,T3 |
| StKeyMgrErrKeyNotValid |
647 |
Covered |
T4,T17,T20 |
| StSw |
428 |
Covered |
T1,T2,T12 |
| StTerminalError |
640 |
Covered |
T3,T5,T6 |
| transitions | Line No. | Covered | Tests |
| StAppCfg->StAppMsg |
450 |
Covered |
T3,T5,T21 |
| StAppCfg->StError |
444 |
Not Covered |
|
| StAppCfg->StKeyMgrErrKeyNotValid |
647 |
Covered |
T4,T17,T20 |
| StAppCfg->StTerminalError |
640 |
Not Covered |
|
| StAppMsg->StAppOutLen |
461 |
Covered |
T21,T24,T25 |
| StAppMsg->StAppProcess |
463 |
Covered |
T21,T22,T23 |
| StAppMsg->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StAppMsg->StTerminalError |
640 |
Covered |
T3,T5,T46 |
| StAppOutLen->StAppProcess |
474 |
Covered |
T21,T24,T25 |
| StAppOutLen->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StAppOutLen->StTerminalError |
640 |
Not Covered |
|
| StAppProcess->StAppWait |
482 |
Covered |
T21,T22,T23 |
| StAppProcess->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StAppProcess->StTerminalError |
640 |
Not Covered |
|
| StAppWait->StIdle |
488 |
Covered |
T21,T22,T23 |
| StAppWait->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StAppWait->StTerminalError |
640 |
Covered |
T7 |
| StError->StErrorAwaitApp |
558 |
Not Covered |
|
| StError->StErrorAwaitSw |
553 |
Covered |
T4,T17,T20 |
| StError->StErrorServiceRejected |
550 |
Not Covered |
|
| StError->StErrorWaitAbsorbed |
568 |
Not Covered |
|
| StError->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StError->StTerminalError |
640 |
Not Covered |
|
| StErrorAwaitApp->StErrorWaitAbsorbed |
594 |
Not Covered |
|
| StErrorAwaitApp->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StErrorAwaitApp->StTerminalError |
640 |
Not Covered |
|
| StErrorAwaitSw->StErrorWaitAbsorbed |
580 |
Covered |
T4,T17,T20 |
| StErrorAwaitSw->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StErrorAwaitSw->StTerminalError |
640 |
Not Covered |
|
| StErrorServiceRejected->StIdle |
618 |
Not Covered |
|
| StErrorServiceRejected->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StErrorServiceRejected->StTerminalError |
640 |
Not Covered |
|
| StErrorWaitAbsorbed->StIdle |
605 |
Covered |
T4,T17,T20 |
| StErrorWaitAbsorbed->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StErrorWaitAbsorbed->StTerminalError |
640 |
Not Covered |
|
| StIdle->StAppCfg |
423 |
Covered |
T3,T4,T5 |
| StIdle->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StIdle->StSw |
428 |
Covered |
T1,T2,T12 |
| StIdle->StTerminalError |
640 |
Covered |
T6,T10,T11 |
| StKeyMgrErrKeyNotValid->StError |
511 |
Covered |
T4,T17,T20 |
| StKeyMgrErrKeyNotValid->StTerminalError |
640 |
Not Covered |
|
| StSw->StIdle |
504 |
Covered |
T1,T2,T12 |
| StSw->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
| StSw->StTerminalError |
640 |
Covered |
T9,T47,T48 |
| StTerminalError->StKeyMgrErrKeyNotValid |
647 |
Not Covered |
|
Branch Coverage for Module :
kmac_app
| Line No. | Total | Covered | Percent |
| Branches |
|
89 |
77 |
86.52 |
| TERNARY |
653 |
3 |
2 |
66.67 |
| IF |
290 |
4 |
3 |
75.00 |
| IF |
305 |
2 |
2 |
100.00 |
| IF |
329 |
4 |
4 |
100.00 |
| IF |
376 |
2 |
2 |
100.00 |
| IF |
385 |
2 |
2 |
100.00 |
| CASE |
420 |
32 |
23 |
71.88 |
| IF |
639 |
2 |
2 |
100.00 |
| IF |
644 |
3 |
3 |
100.00 |
| IF |
659 |
2 |
2 |
100.00 |
| CASE |
689 |
4 |
4 |
100.00 |
| IF |
728 |
3 |
3 |
100.00 |
| IF |
792 |
3 |
3 |
100.00 |
| IF |
817 |
2 |
2 |
100.00 |
| CASE |
862 |
7 |
7 |
100.00 |
| CASE |
906 |
3 |
3 |
100.00 |
| IF |
933 |
8 |
7 |
87.50 |
| CASE |
960 |
3 |
3 |
100.00 |
653 assign err_during_sw_d =
654 (mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}) ? 1'b1 : // set
-1-
==>
655 (st_d == StIdle) ? 1'b0 : // clear
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
290 if (!rst_ni) service_rejected_error <= 1'b 0;
-1-
==>
291 else if (service_rejected_error_set) service_rejected_error <= 1'b 1;
-2-
==>
292 else if (service_rejected_error_clr) service_rejected_error <= 1'b 0;
-3-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Covered |
T4,T17,T20 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
305 if (i == app_id) begin
-1-
306 app_o[i] = '{
==>
307 ready: app_data_ready | fsm_data_ready,
308 done: app_digest_done | fsm_digest_done_q,
309 digest_share0: app_digest[0],
310 digest_share1: app_digest[1],
311 // if fsm asserts done, should be an error case.
312 error: error_i | fsm_digest_done_q | sparse_fsm_error_o
313 | service_rejected_error
314 };
315 end else begin
316 app_o[i] = '{
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
329 if (!rst_ni) app_id <= AppIdxW'(0) ; // Do not select any
-1-
==>
330 else if (clr_appid) app_id <= AppIdxW'(0);
-2-
==>
331 else if (set_appid) app_id <= app_id_d;
-3-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T4,T17,T21 |
| 0 |
0 |
1 |
Covered |
T3,T4,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
376 if (!rst_ni) fsm_digest_done_q <= 1'b 0;
-1-
==>
377 else fsm_digest_done_q <= fsm_digest_done_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
385 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, st_e, StIdle)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
420 unique case (st)
-1-
421 StIdle: begin
422 if (arb_valid) begin
-2-
423 st_d = StAppCfg;
==>
424
425 // choose app_id
426 set_appid = 1'b 1;
427 end else if (sw_cmd_i == CmdStart) begin
-3-
428 st_d = StSw;
==>
429 // Software initiates the sequence
430 cmd_o = CmdStart;
431 end else begin
432 st_d = StIdle;
==>
433 end
434 end
435
436 StAppCfg: begin
437 if (AppCfg[app_id].Mode == AppKMAC &&
-4-
438 prim_mubi_pkg::mubi4_test_false_strict(entropy_ready_i)) begin
439 // Check if the entropy is not configured but it is needed in
440 // `AppCfg[app_id]` (KMAC mode).
441 //
442 // SW is not properly configured, report and not request Hashing
443 // Return the app with errors
444 st_d = StError;
==>
445
446 service_rejected_error_set = 1'b 1;
447
448 end else begin
449 // As Cfg is stable now, it sends cmd
450 st_d = StAppMsg;
==>
451
452 // App initiates the data
453 cmd_o = CmdStart;
454 end
455 end
456
457 StAppMsg: begin
458 mux_sel = SelApp;
459 if (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last) begin
-5-
460 if (AppCfg[app_id].Mode == AppKMAC) begin
-6-
461 st_d = StAppOutLen;
==>
462 end else begin
463 st_d = StAppProcess;
==>
464 end
465 end else begin
466 st_d = StAppMsg;
==>
467 end
468 end
469
470 StAppOutLen: begin
471 mux_sel = SelOutLen;
472
473 if (kmac_valid_o && kmac_ready_i) begin
-7-
474 st_d = StAppProcess;
==>
475 end else begin
476 st_d = StAppOutLen;
==>
477 end
478 end
479
480 StAppProcess: begin
481 cmd_o = CmdProcess;
==>
482 st_d = StAppWait;
483 end
484
485 StAppWait: begin
486 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin
-8-
487 // Send digest to KeyMgr and complete the op
488 st_d = StIdle;
==>
489 cmd_o = CmdDone;
490
491 clr_appid = 1'b 1;
492 end else begin
493 st_d = StAppWait;
==>
494 end
495 end
496
497 StSw: begin
498 mux_sel = SelSw;
499
500 cmd_o = sw_cmd_i;
501 absorbed_o = absorbed_i;
502
503 if (sw_cmd_i == CmdDone) begin
-9-
504 st_d = StIdle;
==>
505 end else begin
506 st_d = StSw;
==>
507 end
508 end
509
510 StKeyMgrErrKeyNotValid: begin
511 st_d = StError;
==>
512
513 // As mux_sel is not set to SelApp, app_data_ready is still 0.
514 // This logic won't accept the requests from the selected App.
515 fsm_err.valid = 1'b 1;
516 fsm_err.code = ErrKeyNotValid;
517 fsm_err.info = 24'(app_id);
518 end
519
520 StError: begin
521 // In this state, the state machine flush out the request
522 st_d = StError;
523
524 // Absorb data on the app interface.
525 fsm_data_ready = ~err_during_sw_q;
526
527 // Next step depends on two conditions:
528 // 1) Error being processed by SW
529 // 2) Last data provided from the app interface (so that the app interface is completely)
530 // drained. If the error occurred during a SW operation, the app interface is not
531 // involved, so this condition gets skipped.
532 unique case ({err_processed_i,
-10-
533 (app_i[app_id].valid && app_i[app_id].last) || err_during_sw_q})
534 2'b00: begin
535 // Error not processed by SW and not last data from app interface -> keep current state.
536 st_d = StError;
==>
537 end
538 2'b01: begin
539 // Error not processed by SW but last data from app interface:
540 // 1. Send garbage digest to the app interface (in the next cycle) to complete the
541 // transaction.
542 fsm_digest_done_d = ~err_during_sw_q;
543 if (service_rejected_error) begin
-11-
544 // 2.a) Service was rejected because an app interface tried to configure KMAC while no
545 // entropy was available. It is assumed that SW is not loaded yet, so don't wait for
546 // SW to process the error. The last data from the app interface has now arrived, but
547 // we don't need to wait for the SHA3 core to have absorbed it because the data never
548 // entered the SHA3 core: the request from the app interface was terminated during the
549 // configuration phase.
550 st_d = StErrorServiceRejected;
==>
551 end else begin
552 // 2.b) If service was not rejected, wait for SW to process the error.
553 st_d = StErrorAwaitSw;
==>
554 end
555 end
556 2'b10: begin
557 // Error processed by SW but not last data from app interface -> wait for app interface.
558 st_d = StErrorAwaitApp;
==>
559 end
560 2'b11: begin
561 // Error processed by SW and last data from app interface:
562 // Send garbage digest to the app interface (in the next cycle) to complete the
563 // transaction.
564 fsm_digest_done_d = ~err_during_sw_q;
==>
565 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
566 // but serves to bring the SHA3 engine back to the idle state).
567 cmd_o = CmdProcess;
568 st_d = StErrorWaitAbsorbed;
569 end
570 default: st_d = StError;
==>
571 endcase
572 end
573
574 StErrorAwaitSw: begin
575 // Just wait for SW to process the error.
576 if (err_processed_i) begin
-12-
577 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
578 // but serves to bring the SHA3 engine back to the idle state).
579 cmd_o = CmdProcess;
==>
580 st_d = StErrorWaitAbsorbed;
581 end
MISSING_ELSE
==>
582 end
583
584 StErrorAwaitApp: begin
585 // Keep absorbing data on the app interface until the last data.
586 fsm_data_ready = 1'b1;
587 if (app_i[app_id].valid && app_i[app_id].last) begin
-13-
588 // Send garbage digest to the app interface (in the next cycle) to complete the
589 // transaction.
590 fsm_digest_done_d = 1'b1;
==>
591 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
592 // but serves to bring the SHA3 engine back to the idle state).
593 cmd_o = CmdProcess;
594 st_d = StErrorWaitAbsorbed;
595 end
MISSING_ELSE
==>
596 end
597
598 StErrorWaitAbsorbed: begin
599 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin
-14-
600 // Clear internal variables, send done command, and return to idle.
601 clr_appid = 1'b1;
602 clear_after_error_o = prim_mubi_pkg::MuBi4True;
603 service_rejected_error_clr = 1'b1;
604 cmd_o = CmdDone;
605 st_d = StIdle;
606 // If error originated from SW, report 'absorbed' to SW.
607 if (err_during_sw_q) begin
-15-
608 absorbed_o = prim_mubi_pkg::MuBi4True;
==>
609 end
MISSING_ELSE
==>
610 end
MISSING_ELSE
==>
611 end
612
613 StErrorServiceRejected: begin
614 // Clear internal variables and return to idle.
615 clr_appid = 1'b1;
==>
616 clear_after_error_o = prim_mubi_pkg::MuBi4True;
617 service_rejected_error_clr = 1'b1;
618 st_d = StIdle;
619 end
620
621 StTerminalError: begin
622 // this state is terminal
623 st_d = st;
==>
624 sparse_fsm_error_o = 1'b 1;
625 fsm_err.valid = 1'b 1;
626 fsm_err.code = ErrFatalError;
627 fsm_err.info = 24'(app_id);
628 end
629
630 default: begin
631 st_d = StTerminalError;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests |
| StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T4,T5 |
| StIdle |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T12 |
| StIdle |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StAppCfg |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StAppCfg |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T4,T5 |
| StAppMsg |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T24,T25 |
| StAppMsg |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T22,T23 |
| StAppMsg |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T5,T21 |
| StAppOutLen |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T24,T25 |
| StAppOutLen |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T24,T26,T27 |
| StAppProcess |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T22,T23 |
| StAppWait |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T22,T23 |
| StAppWait |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T22,T23 |
| StSw |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T12 |
| StSw |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T12 |
| StKeyMgrErrKeyNotValid |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T17,T20 |
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
2'b00 |
- |
- |
- |
- |
- |
Covered |
T4,T17,T20 |
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
2'b01 |
1 |
- |
- |
- |
- |
Not Covered |
|
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
2'b01 |
0 |
- |
- |
- |
- |
Covered |
T4,T17,T20 |
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
2'b10 |
- |
- |
- |
- |
- |
Not Covered |
|
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
2'b11 |
- |
- |
- |
- |
- |
Not Covered |
|
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
default |
- |
- |
- |
- |
- |
Not Covered |
|
| StErrorAwaitSw |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T4,T17,T20 |
| StErrorAwaitSw |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T4,T17,T20 |
| StErrorAwaitApp |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Not Covered |
|
| StErrorAwaitApp |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Not Covered |
|
| StErrorWaitAbsorbed |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
Not Covered |
|
| StErrorWaitAbsorbed |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
Covered |
T4,T17,T20 |
| StErrorWaitAbsorbed |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T4,T17,T20 |
| StErrorServiceRejected |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StTerminalError |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T5,T6 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T6,T10,T11 |
639 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
-1-
640 st_d = StTerminalError;
==>
641 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T5,T6 |
| 0 |
Covered |
T1,T2,T3 |
644 if (st_d != StTerminalError) begin
-1-
645 // Key from keymgr is used but not valid, so abort into the invalid key error state.
646 if (keymgr_key_used && !keymgr_key_i.valid) begin
-2-
647 st_d = StKeyMgrErrKeyNotValid;
==>
648 end
MISSING_ELSE
==>
649 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T4,T17,T20 |
| 1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
Covered |
T3,T5,T6 |
659 if (!rst_ni) begin
-1-
660 err_during_sw_q <= 1'b0;
==>
661 end else begin
662 err_during_sw_q <= err_during_sw_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
689 unique case (mux_sel_buf_kmac)
-1-
690 SelApp: begin
691 // app_id is valid at this time
692 kmac_valid_o = app_i[app_id].valid;
==>
693 kmac_data_o = app_i[app_id].data;
694 // Expand strb to bits. prim_packer inside MSG_FIFO accepts the bit masks
695 for (int i = 0 ; i < $bits(app_i[app_id].strb) ; i++) begin
696 kmac_mask_o[8*i+:8] = {8{app_i[app_id].strb[i]}};
697 end
698 app_data_ready = kmac_ready_i;
699 end
700
701 SelOutLen: begin
702 // Write encoded output length value
703 kmac_valid_o = 1'b 1; // always write
==>
704 kmac_data_o = MsgWidth'(encoded_outlen);
705 kmac_mask_o = MsgWidth'(encoded_outlen_mask);
706 end
707
708 SelSw: begin
709 kmac_valid_o = sw_valid_i;
==>
710 kmac_data_o = sw_data_i ;
711 kmac_mask_o = sw_mask_i ;
712 sw_ready_o = kmac_ready_i ;
713 end
714
715 default: begin // Incl. SelNone
716 kmac_valid_o = 1'b 0;
==>
Branches:
| -1- | Status | Tests |
| SelApp |
Covered |
T3,T5,T21 |
| SelOutLen |
Covered |
T21,T24,T25 |
| SelSw |
Covered |
T1,T2,T12 |
| default |
Covered |
T1,T2,T3 |
728 if (mux_sel_buf_err_check != SelSw && sw_valid_i) begin
-1-
729 // If SW writes message into FIFO
730 mux_err = '{
==>
731 valid: 1'b 1,
732 code: ErrSwPushedMsgFifo,
733 info: 24'({8'h 00, 8'(st), 8'(mux_sel_buf_err_check)})
734 };
735 end else if (app_active_o && sw_cmd_i != CmdNone) begin
-2-
736 // If SW issues command except start
737 mux_err = '{
==>
738 valid: 1'b 1,
739 code: ErrSwIssuedCmdInAppActive,
740 info: 24'(sw_cmd_i)
741 };
742 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T3,T5,T6 |
| 0 |
1 |
Covered |
T28,T29,T30 |
| 0 |
0 |
Covered |
T1,T2,T3 |
792 if ((mux_sel_buf_output == SelSw) &&
-1-
793 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin
794 reg_state_valid = keccak_state_valid_i;
795 reg_state_o = keccak_state_i;
796 // If key is sideloaded and KMAC is SW initiated
797 // hide the capacity from SW by zeroing (see #17508)
798 if (keymgr_key_en_i) begin
-2-
799 for (int i = 0; i < Share; i++) begin
==>
800 unique case (reg_keccak_strength_i)
801 L128: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L128]] = '0;
802 L224: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L224]] = '0;
803 L256: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L256]] = '0;
804 L384: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L384]] = '0;
805 L512: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L512]] = '0;
806 default: reg_state_o[i] = '0;
807 endcase
808 end
809 end
MISSING_ELSE
==>
810 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T31,T32,T22 |
| 1 |
0 |
Covered |
T1,T2,T12 |
| 0 |
- |
Covered |
T1,T2,T3 |
817 if (st == StAppWait && prim_mubi_pkg::mubi4_test_true_strict(absorbed_i) &&
-1-
818 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin
819 // SHA3 engine has calculated the hash. Return the data to KeyMgr
820 app_digest_done = 1'b 1;
==>
821
822 // digest has always 2 entries. If !EnMasking, second is tied to 0.
823 for (int i = 0 ; i < Share ; i++) begin
824 // Return the portion of state.
825 app_digest[i] = keccak_state_i[i][AppDigestW-1:0];
826 end
827 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T21,T22,T23 |
| 0 |
Covered |
T1,T2,T3 |
862 unique case (st)
-1-
863 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin
864 // Key from keymgr is actually used if the current HW app interface does *keyed* MAC.
865 keymgr_key_used = AppCfg[app_id].Mode == AppKMAC;
==>
866 key_len_o = SideloadedKey;
867 for (int i = 0 ; i < Share; i++) begin
868 key_data_o[i] = keymgr_key[i];
869 end
870 // Key is valid if the current HW app interface does *keyed* MAC and the key provided by
871 // keymgr is valid.
872 key_valid_o = keymgr_key_used && keymgr_key_i.valid;
873 end
874
875 StSw: begin
876 if (keymgr_key_en_i) begin
-2-
877 // Key from keymgr is actually used if *keyed* MAC is enabled.
878 keymgr_key_used = kmac_en_o;
==>
879 key_len_o = SideloadedKey;
880 for (int i = 0 ; i < Share; i++) begin
881 key_data_o[i] = keymgr_key[i];
882 end
883 end
MISSING_ELSE
==>
884 // Key is valid if SW does *keyed* MAC and ...
885 if (kmac_en_o) begin
-3-
886 if (!keymgr_key_en_i) begin
-4-
887 // ... it uses the key from kmac's CSR, or ...
888 key_valid_o = 1'b1;
==>
889 end else begin
890 // ... it uses the key provided by keymgr and that one is valid.
891 key_valid_o = keymgr_key_i.valid;
==>
892 end
893 end
MISSING_ELSE
==>
894 end
895
896 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait |
- |
- |
- |
Covered |
T3,T4,T5 |
| StSw |
1 |
- |
- |
Covered |
T31,T32,T22 |
| StSw |
0 |
- |
- |
Covered |
T1,T2,T12 |
| StSw |
- |
1 |
1 |
Covered |
T1,T2,T12 |
| StSw |
- |
1 |
0 |
Covered |
T22,T25,T26 |
| StSw |
- |
0 |
- |
Covered |
T14,T16,T18 |
| default |
- |
- |
- |
Covered |
T1,T2,T3 |
906 unique case (st)
-1-
907 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin
908 // Check app intf cfg
909 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin
==>
910 if (app_id == i) begin
911 if (AppCfg[i].PrefixMode == 1'b 0) begin
912 sha3_prefix_o = reg_prefix_i;
913 end else begin
914 sha3_prefix_o = AppCfg[i].Prefix;
915 end
916 end
917 end
918 end
919
920 StSw: begin
921 sha3_prefix_o = reg_prefix_i;
==>
922 end
923
924 default: begin
925 sha3_prefix_o = reg_prefix_i;
==>
Branches:
| -1- | Status | Tests |
| StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait |
Covered |
T3,T4,T5 |
| StSw |
Covered |
T1,T2,T12 |
| default |
Covered |
T1,T2,T3 |
933 if (!rst_ni) begin
-1-
934 kmac_en_o <= 1'b 0;
==>
935 sha3_mode_o <= sha3_pkg::Sha3;
936 keccak_strength_o <= sha3_pkg::L256;
937 end else if (clr_appid) begin
-2-
938 // As App completed, latch reg value
939 kmac_en_o <= reg_kmac_en_i;
==>
940 sha3_mode_o <= reg_sha3_mode_i;
941 keccak_strength_o <= reg_keccak_strength_i;
942 end else if (set_appid) begin
-3-
943 kmac_en_o <= AppCfg[arb_idx].Mode == AppKMAC ? 1'b 1 : 1'b 0;
-4-
==>
==>
944 sha3_mode_o <= AppCfg[arb_idx].Mode == AppSHA3
945 ? sha3_pkg::Sha3 : sha3_pkg::CShake;
-5-
==>
==>
946 keccak_strength_o <= AppCfg[arb_idx].Strength ;
947 end else if (st == StIdle) begin
-6-
948 kmac_en_o <= reg_kmac_en_i;
==>
949 sha3_mode_o <= reg_sha3_mode_i;
950 keccak_strength_o <= reg_keccak_strength_i;
951 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
Covered |
T4,T17,T21 |
| 0 |
0 |
1 |
1 |
- |
- |
Covered |
T4,T5,T17 |
| 0 |
0 |
1 |
0 |
- |
- |
Covered |
T3,T21,T22 |
| 0 |
0 |
1 |
- |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
- |
0 |
- |
Covered |
T3,T4,T5 |
| 0 |
0 |
0 |
- |
- |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
- |
- |
0 |
Covered |
T1,T2,T3 |
960 priority casez ({fsm_err.valid, mux_err.valid})
-1-
961 2'b ?1: error_o = mux_err;
==>
962 2'b 10: error_o = fsm_err;
==>
963 default: error_o = '{valid: 1'b0, code: ErrNone, info: '0};
==>
Branches:
| -1- | Status | Tests |
| 2'bz1 |
Covered |
T3,T5,T6 |
| 2'b10 |
Covered |
T3,T4,T5 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
kmac_app
Assertion Details
AppIntfInRange_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
663 |
663 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
SideloadKeySameToDigest_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
663 |
663 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
570654578 |
570514117 |
0 |
0 |
| T1 |
2409 |
2342 |
0 |
0 |
| T2 |
2815 |
2730 |
0 |
0 |
| T3 |
3648 |
3511 |
0 |
0 |
| T4 |
30690 |
30631 |
0 |
0 |
| T5 |
3717 |
3570 |
0 |
0 |
| T12 |
7564 |
7466 |
0 |
0 |
| T13 |
3385 |
3308 |
0 |
0 |
| T14 |
73090 |
73010 |
0 |
0 |
| T15 |
4569 |
4494 |
0 |
0 |
| T19 |
1206 |
1138 |
0 |
0 |
Cover Directives for Properties: Details
AppIntfUseDifferentSizeKey_C
| Name | Attempts | Matches | Incomplete |
| Total |
570654578 |
2944 |
0 |
| T4 |
30690 |
3 |
0 |
| T5 |
3717 |
1 |
0 |
| T12 |
7564 |
0 |
0 |
| T13 |
3385 |
0 |
0 |
| T14 |
73090 |
0 |
0 |
| T15 |
4569 |
0 |
0 |
| T16 |
57447 |
0 |
0 |
| T17 |
43896 |
5 |
0 |
| T18 |
104315 |
0 |
0 |
| T20 |
0 |
8 |
0 |
| T21 |
0 |
64 |
0 |
| T24 |
0 |
64 |
0 |
| T25 |
0 |
1 |
0 |
| T26 |
0 |
15 |
0 |
| T41 |
0 |
6 |
0 |
| T49 |
3442 |
0 |
0 |
| T50 |
0 |
11 |
0 |
