Line Coverage for Module :
kmac_core
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 69 | 68 | 98.55 |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| ALWAYS | 161 | 3 | 3 | 100.00 |
| ALWAYS | 166 | 30 | 30 | 100.00 |
| CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 253 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 265 | 1 | 1 | 100.00 |
| ALWAYS | 268 | 6 | 5 | 83.33 |
| CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
| ALWAYS | 307 | 6 | 6 | 100.00 |
| ALWAYS | 338 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 372 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 394 | 1 | 1 | 100.00 |
| ALWAYS | 420 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
152 logic unused_signals;
153 1/1 assign unused_signals = ^{mode_i, key_valid_i};
Tests: T1 T2 T3
154
155 /////////
156 // FSM //
157 /////////
158 kmac_st_e st, st_d;
159
160 // State register
161 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, kmac_st_e, StKmacIdle)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, kmac_st_e, StKmacIdle):
161.1 `ifdef SIMULATION
161.2 prim_sparse_fsm_flop #(
161.3 .StateEnumT(kmac_st_e),
161.4 .Width($bits(kmac_st_e)),
161.5 .ResetValue($bits(kmac_st_e)'(StKmacIdle)),
161.6 .EnableAlertTriggerSVA(1),
161.7 .CustomForceName("st")
161.8 ) u_state_regs (
161.9 .clk_i ( clk_i ),
161.10 .rst_ni ( rst_ni ),
161.11 .state_i ( st_d ),
161.12 .state_o ( )
161.13 );
161.14 always_ff @(posedge clk_i or negedge rst_ni) begin
161.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
161.16 1/1 st <= StKmacIdle;
Tests: T1 T2 T3
161.17 end else begin
161.18 1/1 st <= st_d;
Tests: T1 T2 T3
161.19 end
161.20 end
161.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (st === u_state_regs.state_o))
161.22 else begin
161.23 `ifdef UVM
161.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
161.25 "../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv", 161, "", 1);
161.26 `else
161.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
161.28 `PRIM_STRINGIFY(u_state_regs_A));
161.29 `endif
161.30 end
161.31 `else
161.32 prim_sparse_fsm_flop #(
161.33 .StateEnumT(kmac_st_e),
161.34 .Width($bits(kmac_st_e)),
161.35 .ResetValue($bits(kmac_st_e)'(StKmacIdle)),
161.36 .EnableAlertTriggerSVA(1)
161.37 ) u_state_regs (
161.38 .clk_i ( `PRIM_FLOP_CLK ),
161.39 .rst_ni ( `PRIM_FLOP_RST ),
161.40 .state_i ( st_d ),
161.41 .state_o ( st )
161.42 );
161.43 `endif162
163 // Next state and output logic
164 // SEC_CM: FSM.SPARSE
165 always_comb begin
166 1/1 st_d = st;
Tests: T1 T2 T3
167
168 1/1 en_kmac_datapath = 1'b 0;
Tests: T1 T2 T3
169 1/1 en_key_write = 1'b 0;
Tests: T1 T2 T3
170
171 1/1 clr_keyidx = 1'b 0;
Tests: T1 T2 T3
172
173 1/1 kmac_valid = 1'b 0;
Tests: T1 T2 T3
174 1/1 kmac_process = 1'b 0;
Tests: T1 T2 T3
175
176 1/1 sparse_fsm_error_o = 1'b 0;
Tests: T1 T2 T3
177
178 1/1 unique case (st)
Tests: T1 T2 T3
179 StKmacIdle: begin
180 1/1 if (kmac_en_i && start_i) begin
Tests: T1 T2 T3
181 1/1 st_d = StKey;
Tests: T1 T2 T4
182 end else begin
183 1/1 st_d = StKmacIdle;
Tests: T1 T2 T3
184 end
185 end
186
187 // If State enters here, regardless of the `process_i`, the state writes
188 // full block size of the key into SHA3 hashing engine.
189 StKey: begin
190 1/1 en_kmac_datapath = 1'b 1;
Tests: T1 T2 T4
191 1/1 en_key_write = 1'b 1;
Tests: T1 T2 T4
192
193 1/1 if (sent_blocksize) begin
Tests: T1 T2 T4
194 1/1 st_d = StKmacMsg;
Tests: T1 T2 T4
195
196 1/1 kmac_valid = 1'b 0;
Tests: T1 T2 T4
197 1/1 clr_keyidx = 1'b 1;
Tests: T1 T2 T4
198 end else begin
199 1/1 st_d = StKey;
Tests: T1 T2 T4
200
201 1/1 kmac_valid = 1'b 1;
Tests: T1 T2 T4
202 end
203 end
204
205 StKmacMsg: begin
206 // If process is previously latched, it is sent to SHA3 here.
207 1/1 if (process_i || process_latched) begin
Tests: T1 T2 T4
208 1/1 st_d = StKmacFlush;
Tests: T1 T2 T4
209
210 1/1 kmac_process = 1'b 1;
Tests: T1 T2 T4
211 end else begin
212 1/1 st_d = StKmacMsg;
Tests: T1 T2 T4
213 end
214 end
215
216 StKmacFlush: begin
217 1/1 if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
Tests: T1 T2 T4
218 1/1 st_d = StKmacIdle;
Tests: T1 T2 T4
219 end else begin
220 1/1 st_d = StKmacFlush;
Tests: T1 T2 T4
221 end
222 end
223
224 StTerminalError: begin
225 // this state is terminal
226 1/1 st_d = st;
Tests: T3 T5 T6
227 1/1 sparse_fsm_error_o = 1'b 1;
Tests: T3 T5 T6
228 end
229
230 default: begin
231 // this state is terminal
232 st_d = StTerminalError;
233 sparse_fsm_error_o = 1'b 1;
234 end
235 endcase
236
237 // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC
238 // Unconditionally jump into the terminal error state
239 // if the life cycle controller triggers an escalation.
240 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
Tests: T1 T2 T3
241 1/1 st_d = StTerminalError;
Tests: T3 T5 T6
242 end
MISSING_ELSE
243 end
244
245 //////////////
246 // Datapath //
247 //////////////
248
249 // DATA Mux depending on kmac_en
250 // When Key write happens, hold the FIFO request. so fifo_ready_o is tied to 0
251 1/1 assign msg_valid_o = (en_kmac_datapath) ? kmac_valid : fifo_valid_i;
Tests: T1 T2 T3
252 1/1 assign msg_data_o = (en_kmac_datapath) ? kmac_data : fifo_data_i ;
Tests: T1 T2 T3
253 1/1 assign msg_strb_o = (en_kmac_datapath) ? kmac_strb : fifo_strb_i ;
Tests: T1 T2 T3
254 1/1 assign fifo_ready_o = (en_kmac_datapath) ? 1'b 0 : msg_ready_i ;
Tests: T1 T2 T3
255
256 // secret key write request to SHA3 hashing engine is always full width write.
257 // KeyMgr is fixed 256 bit output. So `right_encode(256)` is 0x020100 --> strb 3
258 1/1 assign kmac_strb = (en_key_write ) ? '1 : '0;
Tests: T1 T2 T3
259
260 1/1 assign kmac_data = (en_key_write) ? key_sliced : '{default:'0};
Tests: T1 T2 T3
261
262 // Process is controlled by the KMAC core always.
263 // This is mainly to prevent process_i asserted while KMAC core is writing
264 // the secret key to SHA3 hashing engine (the empty message case)
265 1/1 assign process_o = (kmac_en_i) ? kmac_process : process_i ;
Tests: T1 T2 T3
266
267 always_ff @(posedge clk_i or negedge rst_ni) begin
268 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
269 1/1 process_latched <= 1'b 0;
Tests: T1 T2 T3
270 1/1 end else if (process_i && !process_o) begin
Tests: T1 T2 T3
271 0/1 ==> process_latched <= 1'b 1;
272 1/1 end else if (process_o ||
Tests: T1 T2 T3
273 prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
274 1/1 process_latched <= 1'b 0;
Tests: T1 T2 T4
275 end
MISSING_ELSE
276 end
277
278 // bytepad(encode_string(K), 168 or 136) =====================================
279 // 1. Prepare left_encode(w)
280 // 2. Prepare left_encode(len(secret_key))
281 // 3. Concatenate left_encode(len(secret_key)) || secret_key
282 // 4. Concaatenate left_encode(w) || encode_string(secret_key)
283 // 5. Based on the address, slice out the data into MsgWidth bits
284
285 // left_encode(w): Same as used in sha3pad logic.
286 logic [15:0] encode_bytepad;
287 1/1 assign encode_bytepad = sha3_pkg::encode_bytepad_len(strength_i);
Tests: T1 T2 T3
288
289 // left_encode(len(secret_key))
290 // encoded length is always byte size. Use MaxEncodedKeyLenByte parameter
291 // from kmac_pkg and add one more byte to indicate how many bytes used to
292 // represent len(secret_key)
293 // Note that if the secret_key is 128 bit, only lower 16 bits of
294 // `encode_keylen` are valid. Refer `encoded_key` concatenation logic below.
295 // As the encoded string in the spec big-endian, The endian swap is a must.
296 logic [MaxEncodedKeyLenSize + 8 - 1:0] encode_keylen [Share];
297
298 always_comb begin
299 // the spec mentioned the key length is encoded in left_encode()
300 // The number is represented in big-endian. For example:
301 // 384 ==> 0x02 0x01 0x80
302 // The first byte is the number of bytes to represent 384
303 // The second byte represents 2**8 number, which is 256 here.
304 // The third byte represents 2**0 number, which is 128.
305 // The data put into MsgFIFO is little-endian and SHA3(Keccak) processes in
306 // little-endian. So, below keylen swaps the byte order
307 1/1 unique case (key_len_i)
Tests: T1 T2 T3
308 // endian-swapped key_length num_bytes
309 // Key128: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(128)}}, 8'h 01};
310 // Key192: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(192)}}, 8'h 01};
311 // Key256: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(256)}}, 8'h 02};
312 // Key384: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(384)}}, 8'h 02};
313 // Key512: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(512)}}, 8'h 02};
314
315 // Vivado does not support stream swap for non context value. So assign
316 // the value directly.
317 1/1 Key128: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 0080_01);
Tests: T1 T2 T3
318 1/1 Key192: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 00C0_01);
Tests: T4 T14 T5
319 1/1 Key256: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 0001_02);
Tests: T1 T2 T3
320 1/1 Key384: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 8001_02);
Tests: T3 T14 T16
321 1/1 Key512: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 0002_02);
Tests: T4 T14 T15
322 default: encode_keylen[0] = '0;
323 endcase
324 end
325
326 if (EnMasking) begin: gen_encode_keylen_masked
327 assign encode_keylen[1] = '0;
328 end
329
330 // encode_string(secret_key): Concatenate key
331 // Based on the left_encode(len(secret_key)) size, the concatenation logic
332 // should be changed. If key length is 128 bit, only lower 16 bits of the
333 // encoded length are used so that the upper 8 bits are padded with 0 as
334 // defined in bytepad() function.
335
336 for (genvar i = 0 ; i < Share; i++) begin : gen_encoded_key
337 always_comb begin
338 1/1 unique case (key_len_i)
Tests: T1 T2 T3
339 // In Key 128, 192 case, only lower parts of encode_keylen signal is
340 // used. So upper padding requires 8 more bits than MaxKeyLen - keylen
341 1/1 Key128: encoded_key[i] = {(8 + MaxKeyLen - 128)'(0),
Tests: T1 T2 T3
342 key_data_i[i][0+:128],
343 encode_keylen[i][0+:MaxEncodedKeyLenSize]};
344
345 1/1 Key192: encoded_key[i] = {(8 + MaxKeyLen - 192)'(0),
Tests: T4 T14 T5
346 key_data_i[i][0+:192],
347 encode_keylen[i][0+:MaxEncodedKeyLenSize]};
348
349 1/1 Key256: encoded_key[i] = {(MaxKeyLen - 256)'(0),
Tests: T1 T2 T3
350 key_data_i[i][0+:256],
351 encode_keylen[i]};
352
353 1/1 Key384: encoded_key[i] = {(MaxKeyLen - 384)'(0),
Tests: T3 T14 T16
354 key_data_i[i][0+:384],
355 encode_keylen[i]};
356
357 // Assume 512bit is the MaxKeyLen
358 1/1 Key512: encoded_key[i] = {key_data_i[i][0+:512],
Tests: T4 T14 T15
359 encode_keylen[i]};
360
361 default: encoded_key[i] = '0;
362 endcase
363 end
364 end : gen_encoded_key
365
366 // Above logic assumes MaxKeyLen as 512 bits. Revise if it is not.
367 `ASSERT_INIT(MaxKeyLenMatchToKey512_A, kmac_pkg::MaxKeyLen == 512)
368
369 // Combine the bytepad `left_encode(w)` and the `encode_string(secret_key)`
370 logic [MaxEncodedKeyW + 16 -1 :0] encoded_key_block [Share];
371
372 1/1 assign encoded_key_block[0] = {encoded_key[0], encode_bytepad};
Tests: T1 T2 T3
373
374 if (EnMasking) begin : gen_encoded_key_block_masked
375 assign encoded_key_block[1] = {encoded_key[1], 16'h 0};
376 end
377
378 // Slicer to slice out 64 bits
379 for (genvar i = 0 ; i < Share ; i++) begin : gen_key_slicer
380 prim_slicer #(
381 .InW (MaxEncodedKeyW+16),
382 .IndexW(KeccakMsgAddrW),
383 .OutW(MsgWidth)
384 ) u_key_slicer (
385 .sel_i (key_index),
386 .data_i (encoded_key_block[i]),
387 .data_o (key_sliced[i])
388 );
389 end
390
391 // `key_index` logic
392 // key_index is used to select MsgWidth data from long `encoded_key_block`
393 // It behaves same as `keccak_addr` or `prefix_index` in sha3pad module.
394 1/1 assign inc_keyidx = kmac_valid & msg_ready_i ;
Tests: T1 T2 T3
395
396 // This primitive is used to place a hardened counter
397 // SEC_CM: CTR.REDUN
398 prim_count #(
399 .Width(sha3_pkg::KeccakMsgAddrW)
400 ) u_key_index_count (
401 .clk_i,
402 .rst_ni,
403 .clr_i(clr_keyidx),
404 .set_i(1'b0),
405 .set_cnt_i('0),
406 .incr_en_i(inc_keyidx),
407 .decr_en_i(1'b0),
408 .step_i(sha3_pkg::KeccakMsgAddrW'(1)),
409 .commit_i(1'b1),
410 .cnt_o(key_index),
411 .cnt_after_commit_o(),
412 .err_o(key_index_error_o)
413 );
414
415 // Block size based on the address.
416 // This is used for bytepad() and also pad10*1()
417 // assign block_addr_limit = KeccakRate[strength_i];
418 // but below is easier to understand
419 always_comb begin
420 1/1 unique case (strength_i)
Tests: T1 T2 T3
421 1/1 L128: block_addr_limit = KeccakCountW'(KeccakRate[L128]);
Tests: T1 T2 T3
422 1/1 L224: block_addr_limit = KeccakCountW'(KeccakRate[L224]);
Tests: T40 T79 T51
423 1/1 L256: block_addr_limit = KeccakCountW'(KeccakRate[L256]);
Tests: T1 T2 T3
424 1/1 L384: block_addr_limit = KeccakCountW'(KeccakRate[L384]);
Tests: T4 T5 T95
425 1/1 L512: block_addr_limit = KeccakCountW'(KeccakRate[L512]);
Tests: T14 T18 T40
426
427 default: block_addr_limit = '0;
428 endcase
429 end
430
431 1/1 assign sent_blocksize = (key_index == block_addr_limit);
Tests: T1 T2 T3
Cond Coverage for Module :
kmac_core
| Total | Covered | Percent |
|---|
| Conditions | 28 | 26 | 92.86 |
| Logical | 28 | 26 | 92.86 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 180
EXPRESSION (kmac_en_i && start_i)
----1---- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T14,T16 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 207
EXPRESSION (process_i || process_latched)
----1---- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T4 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T4 |
LINE 251
EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 252
EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 253
EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 254
EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 258
EXPRESSION (en_key_write ? '1 : '0)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 260
EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 265
EXPRESSION (kmac_en_i ? kmac_process : process_i)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 270
EXPRESSION (process_i && ((!process_o)))
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Not Covered | |
LINE 394
EXPRESSION (kmac_valid & msg_ready_i)
-----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 431
EXPRESSION (key_index == block_addr_limit)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
FSM Coverage for Module :
kmac_core
Summary for FSM :: st
| Total | Covered | Percent | |
| States |
5 |
5 |
100.00 |
(Not included in score) |
| Transitions |
8 |
8 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st
| states | Line No. | Covered | Tests |
| StKey |
181 |
Covered |
T1,T2,T4 |
| StKmacFlush |
208 |
Covered |
T1,T2,T4 |
| StKmacIdle |
183 |
Covered |
T1,T2,T3 |
| StKmacMsg |
194 |
Covered |
T1,T2,T4 |
| StTerminalError |
241 |
Covered |
T3,T5,T6 |
| transitions | Line No. | Covered | Tests |
| StKey->StKmacMsg |
194 |
Covered |
T1,T2,T4 |
| StKey->StTerminalError |
241 |
Covered |
T5,T8,T99 |
| StKmacFlush->StKmacIdle |
218 |
Covered |
T1,T2,T4 |
| StKmacFlush->StTerminalError |
241 |
Covered |
T66,T67 |
| StKmacIdle->StKey |
181 |
Covered |
T1,T2,T4 |
| StKmacIdle->StTerminalError |
241 |
Covered |
T3,T6,T10 |
| StKmacMsg->StKmacFlush |
208 |
Covered |
T1,T2,T4 |
| StKmacMsg->StTerminalError |
241 |
Covered |
T9,T101,T102 |
Branch Coverage for Module :
kmac_core
| Line No. | Total | Covered | Percent |
| Branches |
|
50 |
46 |
92.00 |
| TERNARY |
251 |
2 |
2 |
100.00 |
| TERNARY |
252 |
2 |
2 |
100.00 |
| TERNARY |
253 |
2 |
2 |
100.00 |
| TERNARY |
254 |
2 |
2 |
100.00 |
| TERNARY |
258 |
2 |
2 |
100.00 |
| TERNARY |
260 |
2 |
2 |
100.00 |
| TERNARY |
265 |
2 |
2 |
100.00 |
| IF |
161 |
2 |
2 |
100.00 |
| CASE |
178 |
10 |
10 |
100.00 |
| IF |
240 |
2 |
2 |
100.00 |
| IF |
268 |
4 |
3 |
75.00 |
| CASE |
307 |
6 |
5 |
83.33 |
| CASE |
420 |
6 |
5 |
83.33 |
| CASE |
338 |
6 |
5 |
83.33 |
251 assign msg_valid_o = (en_kmac_datapath) ? kmac_valid : fifo_valid_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
252 assign msg_data_o = (en_kmac_datapath) ? kmac_data : fifo_data_i ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
253 assign msg_strb_o = (en_kmac_datapath) ? kmac_strb : fifo_strb_i ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
254 assign fifo_ready_o = (en_kmac_datapath) ? 1'b 0 : msg_ready_i ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
258 assign kmac_strb = (en_key_write ) ? '1 : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
260 assign kmac_data = (en_key_write) ? key_sliced : '{default:'0};
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
265 assign process_o = (kmac_en_i) ? kmac_process : process_i ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
161 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, kmac_st_e, StKmacIdle)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
178 unique case (st)
-1-
179 StKmacIdle: begin
180 if (kmac_en_i && start_i) begin
-2-
181 st_d = StKey;
==>
182 end else begin
183 st_d = StKmacIdle;
==>
184 end
185 end
186
187 // If State enters here, regardless of the `process_i`, the state writes
188 // full block size of the key into SHA3 hashing engine.
189 StKey: begin
190 en_kmac_datapath = 1'b 1;
191 en_key_write = 1'b 1;
192
193 if (sent_blocksize) begin
-3-
194 st_d = StKmacMsg;
==>
195
196 kmac_valid = 1'b 0;
197 clr_keyidx = 1'b 1;
198 end else begin
199 st_d = StKey;
==>
200
201 kmac_valid = 1'b 1;
202 end
203 end
204
205 StKmacMsg: begin
206 // If process is previously latched, it is sent to SHA3 here.
207 if (process_i || process_latched) begin
-4-
208 st_d = StKmacFlush;
==>
209
210 kmac_process = 1'b 1;
211 end else begin
212 st_d = StKmacMsg;
==>
213 end
214 end
215
216 StKmacFlush: begin
217 if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
-5-
218 st_d = StKmacIdle;
==>
219 end else begin
220 st_d = StKmacFlush;
==>
221 end
222 end
223
224 StTerminalError: begin
225 // this state is terminal
226 st_d = st;
==>
227 sparse_fsm_error_o = 1'b 1;
228 end
229
230 default: begin
231 // this state is terminal
232 st_d = StTerminalError;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
| StKmacIdle |
1 |
- |
- |
- |
Covered |
T1,T2,T4 |
| StKmacIdle |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
| StKey |
- |
1 |
- |
- |
Covered |
T1,T2,T4 |
| StKey |
- |
0 |
- |
- |
Covered |
T1,T2,T4 |
| StKmacMsg |
- |
- |
1 |
- |
Covered |
T1,T2,T4 |
| StKmacMsg |
- |
- |
0 |
- |
Covered |
T1,T2,T4 |
| StKmacFlush |
- |
- |
- |
1 |
Covered |
T1,T2,T4 |
| StKmacFlush |
- |
- |
- |
0 |
Covered |
T1,T2,T4 |
| StTerminalError |
- |
- |
- |
- |
Covered |
T3,T5,T6 |
| default |
- |
- |
- |
- |
Covered |
T6,T10,T11 |
240 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
-1-
241 st_d = StTerminalError;
==>
242 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T5,T6 |
| 0 |
Covered |
T1,T2,T3 |
268 if (!rst_ni) begin
-1-
269 process_latched <= 1'b 0;
==>
270 end else if (process_i && !process_o) begin
-2-
271 process_latched <= 1'b 1;
==>
272 end else if (process_o ||
-3-
273 prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
274 process_latched <= 1'b 0;
==>
275 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Covered |
T1,T2,T4 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
307 unique case (key_len_i)
-1-
308 // endian-swapped key_length num_bytes
309 // Key128: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(128)}}, 8'h 01};
310 // Key192: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(192)}}, 8'h 01};
311 // Key256: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(256)}}, 8'h 02};
312 // Key384: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(384)}}, 8'h 02};
313 // Key512: encode_keylen[0] = {{<<8{MaxEncodedKeyLenSize'(512)}}, 8'h 02};
314
315 // Vivado does not support stream swap for non context value. So assign
316 // the value directly.
317 Key128: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 0080_01);
==>
318 Key192: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 00C0_01);
==>
319 Key256: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 0001_02);
==>
320 Key384: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 8001_02);
==>
321 Key512: encode_keylen[0] = (MaxEncodedKeyLenSize+8)'('h 0002_02);
==>
322 default: encode_keylen[0] = '0;
==>
Branches:
| -1- | Status | Tests |
| Key128 |
Covered |
T1,T2,T3 |
| Key192 |
Covered |
T4,T14,T5 |
| Key256 |
Covered |
T1,T2,T3 |
| Key384 |
Covered |
T3,T14,T16 |
| Key512 |
Covered |
T4,T14,T15 |
| default |
Not Covered |
|
420 unique case (strength_i)
-1-
421 L128: block_addr_limit = KeccakCountW'(KeccakRate[L128]);
==>
422 L224: block_addr_limit = KeccakCountW'(KeccakRate[L224]);
==>
423 L256: block_addr_limit = KeccakCountW'(KeccakRate[L256]);
==>
424 L384: block_addr_limit = KeccakCountW'(KeccakRate[L384]);
==>
425 L512: block_addr_limit = KeccakCountW'(KeccakRate[L512]);
==>
426
427 default: block_addr_limit = '0;
==>
Branches:
| -1- | Status | Tests |
| L128 |
Covered |
T1,T2,T3 |
| L224 |
Covered |
T40,T79,T51 |
| L256 |
Covered |
T1,T2,T3 |
| L384 |
Covered |
T4,T5,T95 |
| L512 |
Covered |
T14,T18,T40 |
| default |
Not Covered |
|
338 unique case (key_len_i)
-1-
339 // In Key 128, 192 case, only lower parts of encode_keylen signal is
340 // used. So upper padding requires 8 more bits than MaxKeyLen - keylen
341 Key128: encoded_key[i] = {(8 + MaxKeyLen - 128)'(0),
==>
342 key_data_i[i][0+:128],
343 encode_keylen[i][0+:MaxEncodedKeyLenSize]};
344
345 Key192: encoded_key[i] = {(8 + MaxKeyLen - 192)'(0),
==>
346 key_data_i[i][0+:192],
347 encode_keylen[i][0+:MaxEncodedKeyLenSize]};
348
349 Key256: encoded_key[i] = {(MaxKeyLen - 256)'(0),
==>
350 key_data_i[i][0+:256],
351 encode_keylen[i]};
352
353 Key384: encoded_key[i] = {(MaxKeyLen - 384)'(0),
==>
354 key_data_i[i][0+:384],
355 encode_keylen[i]};
356
357 // Assume 512bit is the MaxKeyLen
358 Key512: encoded_key[i] = {key_data_i[i][0+:512],
==>
359 encode_keylen[i]};
360
361 default: encoded_key[i] = '0;
==>
Branches:
| -1- | Status | Tests |
| Key128 |
Covered |
T1,T2,T3 |
| Key192 |
Covered |
T4,T14,T5 |
| Key256 |
Covered |
T1,T2,T3 |
| Key384 |
Covered |
T3,T14,T16 |
| Key512 |
Covered |
T4,T14,T15 |
| default |
Not Covered |
|
Assert Coverage for Module :
kmac_core
Assertion Details
AckOnlyInMessageState_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
570654578 |
6964854 |
0 |
0 |
| T1 |
2409 |
28 |
0 |
0 |
| T2 |
2815 |
53 |
0 |
0 |
| T3 |
3648 |
0 |
0 |
0 |
| T4 |
30690 |
0 |
0 |
0 |
| T5 |
3717 |
0 |
0 |
0 |
| T12 |
7564 |
53 |
0 |
0 |
| T13 |
3385 |
53 |
0 |
0 |
| T14 |
73090 |
0 |
0 |
0 |
| T15 |
4569 |
1 |
0 |
0 |
| T19 |
1206 |
0 |
0 |
0 |
| T31 |
0 |
575 |
0 |
0 |
| T40 |
0 |
65 |
0 |
0 |
| T51 |
0 |
235 |
0 |
0 |
| T80 |
0 |
53 |
0 |
0 |
| T81 |
0 |
28 |
0 |
0 |
KeyDataStableWhenValid_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
570654578 |
327019571 |
0 |
0 |
| T1 |
2409 |
1346 |
0 |
0 |
| T2 |
2815 |
1901 |
0 |
0 |
| T3 |
3648 |
0 |
0 |
0 |
| T4 |
30690 |
0 |
0 |
0 |
| T5 |
3717 |
36 |
0 |
0 |
| T12 |
7564 |
5475 |
0 |
0 |
| T13 |
3385 |
1806 |
0 |
0 |
| T14 |
73090 |
0 |
0 |
0 |
| T15 |
4569 |
2837 |
0 |
0 |
| T19 |
1206 |
0 |
0 |
0 |
| T31 |
0 |
19146 |
0 |
0 |
| T40 |
0 |
8534 |
0 |
0 |
| T80 |
0 |
1821 |
0 |
0 |
| T81 |
0 |
1309 |
0 |
0 |
KeyLengthStableWhenValid_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
570654578 |
327019571 |
0 |
0 |
| T1 |
2409 |
1346 |
0 |
0 |
| T2 |
2815 |
1901 |
0 |
0 |
| T3 |
3648 |
0 |
0 |
0 |
| T4 |
30690 |
0 |
0 |
0 |
| T5 |
3717 |
36 |
0 |
0 |
| T12 |
7564 |
5475 |
0 |
0 |
| T13 |
3385 |
1806 |
0 |
0 |
| T14 |
73090 |
0 |
0 |
0 |
| T15 |
4569 |
2837 |
0 |
0 |
| T19 |
1206 |
0 |
0 |
0 |
| T31 |
0 |
19146 |
0 |
0 |
| T40 |
0 |
8534 |
0 |
0 |
| T80 |
0 |
1821 |
0 |
0 |
| T81 |
0 |
1309 |
0 |
0 |
KmacEnStable_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
570654578 |
21919 |
0 |
0 |
| T1 |
2409 |
1 |
0 |
0 |
| T2 |
2815 |
1 |
0 |
0 |
| T3 |
3648 |
0 |
0 |
0 |
| T4 |
30690 |
5 |
0 |
0 |
| T5 |
3717 |
1 |
0 |
0 |
| T12 |
7564 |
1 |
0 |
0 |
| T13 |
3385 |
1 |
0 |
0 |
| T14 |
73090 |
0 |
0 |
0 |
| T15 |
4569 |
1 |
0 |
0 |
| T17 |
0 |
7 |
0 |
0 |
| T19 |
1206 |
0 |
0 |
0 |
| T31 |
0 |
8 |
0 |
0 |
| T40 |
0 |
15 |
0 |
0 |
MaxKeyLenMatchToKey512_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
663 |
663 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
ModeStable_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
570654578 |
33981 |
0 |
0 |
| T1 |
2409 |
1 |
0 |
0 |
| T2 |
2815 |
1 |
0 |
0 |
| T3 |
3648 |
2 |
0 |
0 |
| T4 |
30690 |
5 |
0 |
0 |
| T5 |
3717 |
1 |
0 |
0 |
| T12 |
7564 |
1 |
0 |
0 |
| T13 |
3385 |
1 |
0 |
0 |
| T14 |
73090 |
0 |
0 |
0 |
| T15 |
4569 |
1 |
0 |
0 |
| T17 |
0 |
7 |
0 |
0 |
| T19 |
1206 |
0 |
0 |
0 |
| T31 |
0 |
8 |
0 |
0 |
ProcessLatchedCleared_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
570654578 |
0 |
0 |
0 |
StrengthStable_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
570654578 |
39748 |
0 |
0 |
| T1 |
2409 |
1 |
0 |
0 |
| T2 |
2815 |
2 |
0 |
0 |
| T3 |
3648 |
3 |
0 |
0 |
| T4 |
30690 |
7 |
0 |
0 |
| T5 |
3717 |
4 |
0 |
0 |
| T12 |
7564 |
2 |
0 |
0 |
| T13 |
3385 |
2 |
0 |
0 |
| T14 |
73090 |
2 |
0 |
0 |
| T15 |
4569 |
1 |
0 |
0 |
| T19 |
1206 |
1 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
570654578 |
570514117 |
0 |
0 |
| T1 |
2409 |
2342 |
0 |
0 |
| T2 |
2815 |
2730 |
0 |
0 |
| T3 |
3648 |
3511 |
0 |
0 |
| T4 |
30690 |
30631 |
0 |
0 |
| T5 |
3717 |
3570 |
0 |
0 |
| T12 |
7564 |
7466 |
0 |
0 |
| T13 |
3385 |
3308 |
0 |
0 |
| T14 |
73090 |
73010 |
0 |
0 |
| T15 |
4569 |
4494 |
0 |
0 |
| T19 |
1206 |
1138 |
0 |
0 |
