Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	572121839	50247021	0	0
DepthKnown_A	572121839	571930673	0	0
RvalidKnown_A	572121839	571930673	0	0
WreadyKnown_A	572121839	571930673	0	0
gen_passthru_fifo.paramCheckPass	878	878	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	50247021	0	0
T1	2409	424	0	0
T2	2815	562	0	0
T3	3648	83	0	0
T4	30690	328	0	0
T5	3717	83	0	0
T12	7564	548	0	0
T13	3385	565	0	0
T14	73090	3513	0	0
T15	4569	102	0	0
T19	1206	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	571930673	0	0
T1	2409	2342	0	0
T2	2815	2730	0	0
T3	3648	3511	0	0
T4	30690	30631	0	0
T5	3717	3570	0	0
T12	7564	7466	0	0
T13	3385	3308	0	0
T14	73090	73010	0	0
T15	4569	4494	0	0
T19	1206	1138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	571930673	0	0
T1	2409	2342	0	0
T2	2815	2730	0	0
T3	3648	3511	0	0
T4	30690	30631	0	0
T5	3717	3570	0	0
T12	7564	7466	0	0
T13	3385	3308	0	0
T14	73090	73010	0	0
T15	4569	4494	0	0
T19	1206	1138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	571930673	0	0
T1	2409	2342	0	0
T2	2815	2730	0	0
T3	3648	3511	0	0
T4	30690	30631	0	0
T5	3717	3570	0	0
T12	7564	7466	0	0
T13	3385	3308	0	0
T14	73090	73010	0	0
T15	4569	4494	0	0
T19	1206	1138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	572121839	106044984	0	0
DepthKnown_A	572121839	571930673	0	0
RvalidKnown_A	572121839	571930673	0	0
WreadyKnown_A	572121839	571930673	0	0
gen_passthru_fifo.paramCheckPass	878	878	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	106044984	0	0
T1	2409	424	0	0
T2	2815	562	0	0
T3	3648	83	0	0
T4	30690	328	0	0
T5	3717	83	0	0
T12	7564	548	0	0
T13	3385	565	0	0
T14	73090	3513	0	0
T15	4569	102	0	0
T19	1206	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	571930673	0	0
T1	2409	2342	0	0
T2	2815	2730	0	0
T3	3648	3511	0	0
T4	30690	30631	0	0
T5	3717	3570	0	0
T12	7564	7466	0	0
T13	3385	3308	0	0
T14	73090	73010	0	0
T15	4569	4494	0	0
T19	1206	1138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	571930673	0	0
T1	2409	2342	0	0
T2	2815	2730	0	0
T3	3648	3511	0	0
T4	30690	30631	0	0
T5	3717	3570	0	0
T12	7564	7466	0	0
T13	3385	3308	0	0
T14	73090	73010	0	0
T15	4569	4494	0	0
T19	1206	1138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	571930673	0	0
T1	2409	2342	0	0
T2	2815	2730	0	0
T3	3648	3511	0	0
T4	30690	30631	0	0
T5	3717	3570	0	0
T12	7564	7466	0	0
T13	3385	3308	0	0
T14	73090	73010	0	0
T15	4569	4494	0	0
T19	1206	1138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0