Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	572121839	3339	0	0
entropy_period_rd_A	572121839	1721	0	0
intr_enable_rd_A	572121839	2472	0	0
prefix_0_rd_A	572121839	1755	0	0
prefix_10_rd_A	572121839	1892	0	0
prefix_1_rd_A	572121839	1802	0	0
prefix_2_rd_A	572121839	1569	0	0
prefix_3_rd_A	572121839	1606	0	0
prefix_4_rd_A	572121839	1705	0	0
prefix_5_rd_A	572121839	1702	0	0
prefix_6_rd_A	572121839	1635	0	0
prefix_7_rd_A	572121839	1792	0	0
prefix_8_rd_A	572121839	1624	0	0
prefix_9_rd_A	572121839	1672	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	3339	0	0
T61	5781	2	0	0
T62	7517	193	0	0
T63	3320	5	0	0
T123	9559	1	0	0
T124	3742	115	0	0
T127	18242	2	0	0
T129	11749	182	0	0
T134	8138	166	0	0
T135	2674	15	0	0
T141	4146	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1721	0	0
T104	6281	62	0	0
T106	4287	22	0	0
T107	6206	25	0	0
T125	16647	105	0	0
T141	4146	15	0	0
T142	7597	22	0	0
T160	6269	44	0	0
T161	2544	3	0	0
T162	2599	9	0	0
T163	7891	26	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	2472	0	0
T104	6281	65	0	0
T106	4287	17	0	0
T107	6206	28	0	0
T125	16647	96	0	0
T128	1232	8	0	0
T141	4146	14	0	0
T160	6269	2	0	0
T161	2544	8	0	0
T162	2599	7	0	0
T164	1639	5	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1755	0	0
T104	6281	23	0	0
T106	4287	4	0	0
T107	6206	28	0	0
T125	16647	75	0	0
T141	4146	12	0	0
T142	7597	17	0	0
T160	6269	31	0	0
T161	2544	6	0	0
T162	2599	9	0	0
T163	7891	20	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1892	0	0
T104	6281	49	0	0
T106	4287	27	0	0
T107	6206	11	0	0
T125	16647	76	0	0
T141	4146	5	0	0
T142	7597	15	0	0
T160	6269	29	0	0
T161	2544	4	0	0
T162	2599	9	0	0
T163	7891	22	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1802	0	0
T104	6281	35	0	0
T106	4287	19	0	0
T107	6206	23	0	0
T125	16647	74	0	0
T130	14733	1	0	0
T141	4146	5	0	0
T142	7597	16	0	0
T160	6269	34	0	0
T161	2544	8	0	0
T162	2599	9	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1569	0	0
T104	6281	31	0	0
T106	4287	28	0	0
T107	6206	11	0	0
T125	16647	71	0	0
T141	4146	6	0	0
T142	7597	13	0	0
T160	6269	12	0	0
T163	7891	20	0	0
T165	44259	237	0	0
T166	5747	22	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1606	0	0
T104	6281	29	0	0
T106	4287	10	0	0
T107	6206	11	0	0
T125	16647	62	0	0
T141	4146	12	0	0
T142	7597	28	0	0
T160	6269	9	0	0
T161	2544	7	0	0
T163	7891	9	0	0
T165	44259	273	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1705	0	0
T104	6281	35	0	0
T106	4287	15	0	0
T107	6206	14	0	0
T125	16647	59	0	0
T141	4146	4	0	0
T142	7597	15	0	0
T160	6269	8	0	0
T161	2544	6	0	0
T162	2599	8	0	0
T163	7891	19	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1702	0	0
T104	6281	17	0	0
T106	4287	12	0	0
T107	6206	26	0	0
T125	16647	60	0	0
T141	4146	1	0	0
T142	7597	13	0	0
T160	6269	18	0	0
T162	2599	2	0	0
T163	7891	24	0	0
T165	44259	237	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1635	0	0
T104	6281	18	0	0
T106	4287	22	0	0
T107	6206	11	0	0
T125	16647	69	0	0
T141	4146	5	0	0
T142	7597	15	0	0
T160	6269	42	0	0
T161	2544	5	0	0
T162	2599	5	0	0
T163	7891	18	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1792	0	0
T104	6281	37	0	0
T106	4287	15	0	0
T107	6206	25	0	0
T125	16647	93	0	0
T141	4146	2	0	0
T142	7597	9	0	0
T160	6269	11	0	0
T161	2544	8	0	0
T162	2599	9	0	0
T163	7891	14	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1624	0	0
T104	6281	18	0	0
T106	4287	22	0	0
T107	6206	10	0	0
T125	16647	60	0	0
T130	14733	1	0	0
T141	4146	3	0	0
T142	7597	18	0	0
T160	6269	9	0	0
T161	2544	10	0	0
T162	2599	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572121839	1672	0	0
T104	6281	28	0	0
T106	4287	14	0	0
T107	6206	14	0	0
T125	16647	67	0	0
T141	4146	1	0	0
T142	7597	12	0	0
T160	6269	39	0	0
T161	2544	14	0	0
T162	2599	8	0	0
T163	7891	13	0	0