Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46227660	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

53170416

1

T1

447

T2

13

T3

194

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53715164	1			T1	335		T2	1		T3	121
values[0x0]	22111376	1			T1	153		T2	26		T3	59
values[0x1]	23571536	1			T1	161		T2	17		T3	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35915874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63482202

1

T1

504

T2

16

T3

201

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	313386	1			T1	2		T5	4		T16	29
valid_sources[0x01]	1073062	1			T1	4		T5	17		T16	43
valid_sources[0x02]	316952	1			T1	3		T5	8		T16	26
valid_sources[0x03]	315467	1			T1	4		T3	1		T5	15
valid_sources[0x04]	317425	1			T1	1		T5	13		T16	28
valid_sources[0x05]	318116	1			T3	2		T5	12		T16	30
valid_sources[0x06]	410939	1			T1	3		T5	8		T16	21
valid_sources[0x07]	318662	1			T1	4		T3	2		T5	17
valid_sources[0x08]	316188	1			T1	3		T5	16		T16	26
valid_sources[0x09]	352326	1			T1	1		T3	1		T5	21
valid_sources[0x0a]	315551	1			T1	1		T5	8		T15	1
valid_sources[0x0b]	1186023	1			T1	2		T5	7		T15	14
valid_sources[0x0c]	320333	1			T1	3		T3	1		T5	11
valid_sources[0x0d]	328311	1			T1	3		T5	6		T15	16
valid_sources[0x0e]	315786	1			T1	8		T5	19		T16	25
valid_sources[0x0f]	317638	1			T1	6		T5	14		T15	13
valid_sources[0x10]	318254	1			T1	1		T3	2		T5	11
valid_sources[0x11]	316411	1			T1	1		T3	1		T5	3
valid_sources[0x12]	317689	1			T1	1		T2	5		T5	6
valid_sources[0x13]	315660	1			T5	13		T16	31		T17	1
valid_sources[0x14]	319252	1			T1	2		T5	21		T15	9
valid_sources[0x15]	318822	1			T1	2		T3	2		T5	10
valid_sources[0x16]	345053	1			T1	4		T5	3		T16	35
valid_sources[0x17]	319960	1			T1	7		T2	3		T3	1
valid_sources[0x18]	318311	1			T1	1		T5	10		T16	28
valid_sources[0x19]	316023	1			T5	19		T15	3		T16	37
valid_sources[0x1a]	341796	1			T1	2		T3	1		T5	7
valid_sources[0x1b]	337420	1			T1	3		T5	11		T15	7
valid_sources[0x1c]	320766	1			T3	1		T5	7		T15	3
valid_sources[0x1d]	349810	1			T1	4		T3	1		T5	12
valid_sources[0x1e]	319290	1			T1	2		T3	1		T5	2
valid_sources[0x1f]	461706	1			T1	2		T3	1		T5	8
valid_sources[0x20]	324996	1			T1	6		T2	4		T5	8
valid_sources[0x21]	319601	1			T1	3		T5	26		T16	27
valid_sources[0x22]	490352	1			T1	6		T3	2		T5	18
valid_sources[0x23]	317239	1			T1	1		T5	3		T16	32
valid_sources[0x24]	345119	1			T1	2		T5	11		T15	6
valid_sources[0x25]	342586	1			T1	3		T3	2		T5	7
valid_sources[0x26]	318276	1			T1	3		T5	15		T16	25
valid_sources[0x27]	315962	1			T1	4		T3	5		T5	10
valid_sources[0x28]	320161	1			T1	2		T3	1		T5	7
valid_sources[0x29]	317957	1			T1	6		T3	2		T5	9
valid_sources[0x2a]	338516	1			T1	1		T5	6		T15	14
valid_sources[0x2b]	319418	1			T1	1		T3	1		T5	5
valid_sources[0x2c]	318471	1			T1	5		T3	5		T5	22
valid_sources[0x2d]	439037	1			T1	6		T3	1		T5	16
valid_sources[0x2e]	377931	1			T1	1		T3	1		T5	12
valid_sources[0x2f]	316575	1			T1	2		T3	2		T5	11
valid_sources[0x30]	317769	1			T1	2		T5	13		T16	29
valid_sources[0x31]	502445	1			T1	4		T5	7		T16	27
valid_sources[0x32]	314372	1			T3	1		T5	15		T16	23
valid_sources[0x33]	435124	1			T1	2		T3	1		T5	7
valid_sources[0x34]	316519	1			T1	4		T5	11		T16	31
valid_sources[0x35]	317597	1			T1	5		T3	1		T5	19
valid_sources[0x36]	409421	1			T3	1		T5	13		T16	33
valid_sources[0x37]	658828	1			T1	1		T3	1		T5	14
valid_sources[0x38]	322088	1			T1	1		T3	5		T5	12
valid_sources[0x39]	380591	1			T1	5		T5	14		T16	35
valid_sources[0x3a]	319731	1			T1	4		T3	1		T5	19
valid_sources[0x3b]	322092	1			T1	3		T5	18		T16	35
valid_sources[0x3c]	318534	1			T1	1		T5	8		T16	26
valid_sources[0x3d]	317207	1			T1	5		T5	7		T16	41
valid_sources[0x3e]	316832	1			T1	4		T3	3		T5	4
valid_sources[0x3f]	317189	1			T1	1		T2	1		T3	2
valid_sources[0x40]	329882	1			T1	1		T3	3		T5	10
valid_sources[0x41]	320249	1			T1	6		T2	1		T5	19
valid_sources[0x42]	781523	1			T1	2		T3	3		T5	6
valid_sources[0x43]	327661	1			T1	2		T5	8		T15	23
valid_sources[0x44]	317869	1			T1	2		T5	8		T15	7
valid_sources[0x45]	316166	1			T1	3		T3	2		T5	14
valid_sources[0x46]	451134	1			T1	5		T3	1		T5	22
valid_sources[0x47]	329201	1			T1	5		T3	3		T5	9
valid_sources[0x48]	379945	1			T1	1		T5	14		T16	25
valid_sources[0x49]	613411	1			T1	2		T2	3		T5	6
valid_sources[0x4a]	400320	1			T3	1		T5	13		T15	3
valid_sources[0x4b]	317422	1			T1	4		T5	17		T16	34
valid_sources[0x4c]	337675	1			T5	5		T16	31		T17	1
valid_sources[0x4d]	318214	1			T1	1		T5	8		T16	39
valid_sources[0x4e]	315381	1			T5	13		T15	3		T16	27
valid_sources[0x4f]	317392	1			T1	6		T5	7		T16	42
valid_sources[0x50]	315578	1			T1	5		T3	4		T5	17
valid_sources[0x51]	355536	1			T1	1		T5	14		T16	21
valid_sources[0x52]	353492	1			T1	7		T3	1		T5	15
valid_sources[0x53]	314790	1			T1	3		T5	11		T15	8
valid_sources[0x54]	314559	1			T1	4		T5	9		T16	34
valid_sources[0x55]	317022	1			T1	4		T5	18		T16	21
valid_sources[0x56]	1230828	1			T1	5		T5	16		T16	23
valid_sources[0x57]	318824	1			T3	1		T5	16		T15	24
valid_sources[0x58]	315690	1			T1	2		T5	12		T16	29
valid_sources[0x59]	532198	1			T1	7		T5	9		T16	40
valid_sources[0x5a]	605894	1			T1	1		T5	9		T16	16
valid_sources[0x5b]	606911	1			T1	1		T3	1		T5	21
valid_sources[0x5c]	319006	1			T1	5		T3	4		T5	6
valid_sources[0x5d]	316594	1			T1	3		T3	2		T5	12
valid_sources[0x5e]	317539	1			T1	2		T5	12		T16	30
valid_sources[0x5f]	1201982	1			T1	2		T3	2		T5	14
valid_sources[0x60]	323784	1			T1	1		T5	25		T15	12
valid_sources[0x61]	317466	1			T1	2		T2	10		T5	14
valid_sources[0x62]	315455	1			T1	1		T3	2		T5	10
valid_sources[0x63]	337987	1			T3	1		T5	5		T16	29
valid_sources[0x64]	317835	1			T1	4		T5	8		T16	26
valid_sources[0x65]	318280	1			T1	3		T2	13		T5	16
valid_sources[0x66]	319263	1			T1	5		T5	10		T16	23
valid_sources[0x67]	376270	1			T1	3		T3	2		T5	8
valid_sources[0x68]	351111	1			T5	4		T16	28		T17	1
valid_sources[0x69]	321458	1			T3	2		T5	11		T16	29
valid_sources[0x6a]	317107	1			T1	8		T5	8		T15	3
valid_sources[0x6b]	316904	1			T3	2		T5	7		T15	14
valid_sources[0x6c]	331303	1			T1	5		T3	2		T5	12
valid_sources[0x6d]	318235	1			T1	3		T3	2		T4	944
valid_sources[0x6e]	317571	1			T1	2		T5	19		T16	32
valid_sources[0x6f]	318313	1			T1	3		T5	4		T16	32
valid_sources[0x70]	320992	1			T3	2		T5	22		T16	29
valid_sources[0x71]	315778	1			T1	6		T5	8		T16	24
valid_sources[0x72]	387965	1			T1	3		T3	2		T5	10
valid_sources[0x73]	435646	1			T3	1		T5	19		T15	1
valid_sources[0x74]	325577	1			T3	1		T5	13		T15	7
valid_sources[0x75]	394801	1			T1	2		T3	1		T5	14
valid_sources[0x76]	326461	1			T1	4		T3	1		T5	12
valid_sources[0x77]	323302	1			T1	1		T5	5		T16	34
valid_sources[0x78]	356575	1			T1	1		T3	1		T5	10
valid_sources[0x79]	318331	1			T5	7		T16	48		T17	1
valid_sources[0x7a]	318280	1			T1	3		T5	6		T16	16
valid_sources[0x7b]	361877	1			T1	6		T3	4		T5	20
valid_sources[0x7c]	654484	1			T1	3		T3	1		T5	22
valid_sources[0x7d]	369724	1			T3	1		T5	19		T16	27
valid_sources[0x7e]	356754	1			T1	5		T5	25		T16	29
valid_sources[0x7f]	427928	1			T1	3		T5	12		T16	24
valid_sources[0x80]	319818	1			T1	1		T5	16		T15	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25370142

1

T1

221

T3

97

T4

277

values[0x0]

all_enables

biggest_size

14649342

1

T1

110

T2

9

T3

49

values[0x1]

all_enables

biggest_size

13150932

1

T1

116

T2

4

T3

48