Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

46251613

1

T1

202

T2

31

T3

43

full_word

53171957

1

T1

447

T2

13

T3

194

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	99423300	1			T1	649		T2	44		T3	237
auto[TlIntgErrCmd]	103	1			T58	5		T104	6		T105	3
auto[TlIntgErrData]	73	1			T58	3		T104	8		T105	4
auto[TlIntgErrBoth]	94	1			T58	2		T104	6		T105	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53720318

1

T1

335

T2

1

T3

121

auto[1]

45703252

1

T1

314

T2

43

T3

116

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	28349681	1			T1	114		T2	1		T3	24
auto[TlIntgErrNone]	partial	auto[1]	17901685	1			T1	88		T2	30		T3	19
auto[TlIntgErrNone]	full_word	auto[0]	25370503	1			T1	221		T3	97		T4	277
auto[TlIntgErrNone]	full_word	auto[1]	27801431	1			T1	226		T2	13		T3	97
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T58	3		T104	5		T105	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T58	1		T104	1		T105	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T105	1		T170	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T58	1		T171	1		T173	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T58	1		T104	4		T105	1
auto[TlIntgErrData]	partial	auto[1]	32	1			T58	2		T104	4		T105	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T170	1		T175	1		T176	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T169	1		T174	1		T177	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T58	1		T104	1		T105	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T58	1		T104	5		T105	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T171	1		T178	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T179	1		T170	2		T168	1