Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sha3
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.14 97.56 88.89 90.91 93.33 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sha3 95.96 97.56 88.89 100.00 93.33 100.00



Module Instance : tb.dut.u_sha3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 97.56 88.89 100.00 93.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.62 91.91 88.51 100.00 83.33 92.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_keccak 81.47 81.77 88.24 100.00 40.00 78.79 100.00
u_pad 97.26 99.42 88.37 100.00 100.00 95.79 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : sha3
Line No.TotalCoveredPercent
TOTAL828097.56
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17911100.00
ALWAYS18455100.00
ALWAYS19833100.00
CONT_ASSIGN20311100.00
ALWAYS20766100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22011100.00
ALWAYS22733100.00
ALWAYS2373838100.00
ALWAYS33233100.00
ALWAYS349121083.33

137 logic round_count_error, msg_count_error; 138 1/1 assign count_error_o = round_count_error | msg_count_error; Tests: T1 T2 T3  139 140 logic sha3_state_error; 141 logic keccak_round_state_error; 142 logic sha3pad_state_error; 143 144 1/1 assign sparse_fsm_error_o = sha3_state_error | keccak_round_state_error | sha3pad_state_error; Tests: T1 T2 T3  145 146 // Keccak rst_storage is asserted unexpectedly 147 logic keccak_storage_rst_error; 148 1/1 assign keccak_storage_rst_error_o = keccak_storage_rst_error; Tests: T1 T2 T3  149 150 ///////////////// 151 // Connections // 152 ///////////////// 153 154 logic keccak_valid; 155 logic [KeccakMsgAddrW-1:0] keccak_addr; 156 logic [MsgWidth-1:0] keccak_data [Share]; 157 logic keccak_ready; 158 159 // Keccak round run signal can be controlled by sha3pad and also by software 160 // after all message feeding is done. it is mainly used for sponge squeezing 161 // operation after absorbing is completed when output length is longer than 162 // the block size. 163 logic keccak_run, sha3pad_keccak_run, sw_keccak_run; 164 logic keccak_run_req_d, keccak_run_req_q; 165 logic keccak_triggered_d, keccak_triggered_q; 166 logic keccak_complete; 167 168 // Announce that we want to run the Keccak core and tell other blocks to go 169 // quiet. Keep holding the REQ until the Keccak core is done with the 170 // processing. The keccak_complete signal is received once the Keccak core 171 // is back in the Idle state and again susceptible to keccak_run. 172 1/1 assign run_req_o = keccak_run_req_d; Tests: T1 T2 T3  173 1/1 assign keccak_run_req_d = Tests: T1 T2 T3  174 sha3pad_keccak_run || sw_keccak_run ? 1'b 1 : 175 keccak_complete ? 1'b 0 : keccak_run_req_q; 176 177 // Trigger the Keccak engine with a single pulse upon receiving the ACK. 178 1/1 assign keccak_run = run_req_o & run_ack_i & ~keccak_triggered_q; Tests: T1 T2 T3  179 1/1 assign keccak_triggered_d = Tests: T1 T2 T3  180 keccak_run ? 1'b 1 : 181 keccak_complete ? 1'b 0 : keccak_triggered_q; 182 183 always_ff @(posedge clk_i or negedge rst_ni) begin 184 1/1 if (!rst_ni) begin Tests: T1 T2 T3  185 1/1 keccak_run_req_q <= 1'b 0; Tests: T1 T2 T3  186 1/1 keccak_triggered_q <= 1'b 0; Tests: T1 T2 T3  187 end else begin 188 1/1 keccak_run_req_q <= keccak_run_req_d; Tests: T1 T2 T3  189 1/1 keccak_triggered_q <= keccak_triggered_d; Tests: T1 T2 T3  190 end 191 end 192 193 // Absorb pulse output : used to generate interrupts 194 // Latch absorbed signal as kmac_keymgr asserts `CmdDone` when it sees 195 // `absorbed` signal. When this signal goes out, the state is still in 196 // `StAbsorb`. Next state is `StSqueeze`. 197 always_ff @(posedge clk_i or negedge rst_ni) begin 198 2/2 if (!rst_ni) absorbed_o <= prim_mubi_pkg::MuBi4False; Tests: T1 T2 T3  | T1 T2 T3  199 1/1 else absorbed_o <= absorbed; Tests: T1 T2 T3  200 end 201 202 // Squeezing output 203 1/1 assign squeezing_o = squeezing; Tests: T1 T2 T3  204 205 // processing 206 always_ff @(posedge clk_i or negedge rst_ni) begin 207 2/2 if (!rst_ni) processing <= 1'b 0; Tests: T1 T2 T3  | T1 T2 T3  208 2/2 else if (process_i) processing <= 1'b 1; Tests: T1 T2 T3  | T1 T4 T5  209 1/1 else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin Tests: T1 T2 T3  210 1/1 processing <= 1'b 0; Tests: T1 T4 T5  211 end MISSING_ELSE 212 end 213 214 1/1 assign block_processed_o = keccak_complete; Tests: T1 T2 T3  215 216 // State connection 217 1/1 assign state_valid_o = state_valid; Tests: T1 T2 T3  218 1/1 assign state_o = state_guarded; Tests: T1 T2 T3  219 220 1/1 assign sha3_fsm_o = sparse2logic(st); Tests: T1 T2 T3  221 222 /////////////////// 223 // State Machine // 224 /////////////////// 225 226 // State Register 227 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse): 227.1 `ifdef SIMULATION 227.2 prim_sparse_fsm_flop #( 227.3 .StateEnumT(sha3_st_sparse_e), 227.4 .Width($bits(sha3_st_sparse_e)), 227.5 .ResetValue($bits(sha3_st_sparse_e)'(StIdle_sparse)), 227.6 .EnableAlertTriggerSVA(1), 227.7 .CustomForceName("st") 227.8 ) u_state_regs ( 227.9 .clk_i ( clk_i ), 227.10 .rst_ni ( rst_ni ), 227.11 .state_i ( st_d ), 227.12 .state_o ( ) 227.13 ); 227.14 always_ff @(posedge clk_i or negedge rst_ni) begin 227.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  227.16 1/1 st <= StIdle_sparse; Tests: T1 T2 T3  227.17 end else begin 227.18 1/1 st <= st_d; Tests: T1 T2 T3  227.19 end 227.20 end 227.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (st === u_state_regs.state_o)) 227.22 else begin 227.23 `ifdef UVM 227.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 227.25 "../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv", 227, "", 1); 227.26 `else 227.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 227.28 `PRIM_STRINGIFY(u_state_regs_A)); 227.29 `endif 227.30 end 227.31 `else 227.32 prim_sparse_fsm_flop #( 227.33 .StateEnumT(sha3_st_sparse_e), 227.34 .Width($bits(sha3_st_sparse_e)), 227.35 .ResetValue($bits(sha3_st_sparse_e)'(StIdle_sparse)), 227.36 .EnableAlertTriggerSVA(1) 227.37 ) u_state_regs ( 227.38 .clk_i ( `PRIM_FLOP_CLK ), 227.39 .rst_ni ( `PRIM_FLOP_RST ), 227.40 .state_i ( st_d ), 227.41 .state_o ( st ) 227.42 ); 227.43 `endif228 229 230 // Next State and Output Logic 231 // Mainly the FSM controls the input signal access 232 // StIdle: only start_i signal is allowed 233 // StAbsorb: only process_i signal is allowed 234 // StSqueeze: only run_i, done_i signal is allowed 235 236 always_comb begin 237 1/1 st_d = st; Tests: T1 T2 T3  238 239 // default output values 240 1/1 keccak_start = 1'b 0; Tests: T1 T2 T3  241 1/1 keccak_process = 1'b 0; Tests: T1 T2 T3  242 1/1 sw_keccak_run = 1'b 0; Tests: T1 T2 T3  243 1/1 keccak_done = prim_mubi_pkg::MuBi4False; Tests: T1 T2 T3  244 245 1/1 squeezing = 1'b 0; Tests: T1 T2 T3  246 247 1/1 state_valid = 1'b 0; Tests: T1 T2 T3  248 1/1 mux_sel = MuxGuard ; Tests: T1 T2 T3  249 250 1/1 sha3_state_error = 1'b 0; Tests: T1 T2 T3  251 252 1/1 unique case (st) Tests: T1 T2 T3  253 StIdle_sparse: begin 254 1/1 if (start_i) begin Tests: T1 T2 T3  255 1/1 st_d = StAbsorb_sparse; Tests: T1 T3 T4  256 257 1/1 keccak_start = 1'b 1; Tests: T1 T3 T4  258 end else begin 259 1/1 st_d = StIdle_sparse; Tests: T1 T2 T3  260 end 261 end 262 263 StAbsorb_sparse: begin 264 1/1 if (process_i && !processing) begin Tests: T1 T3 T4  265 1/1 st_d = StAbsorb_sparse; Tests: T1 T4 T5  266 267 1/1 keccak_process = 1'b 1; Tests: T1 T4 T5  268 1/1 end else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin Tests: T1 T3 T4  269 1/1 st_d = StSqueeze_sparse; Tests: T1 T4 T5  270 end else begin 271 1/1 st_d = StAbsorb_sparse; Tests: T1 T3 T4  272 end 273 end 274 275 StSqueeze_sparse: begin 276 1/1 state_valid = 1'b 1; Tests: T1 T4 T5  277 1/1 mux_sel = MuxRelease; // Expose state to register interface Tests: T1 T4 T5  278 279 1/1 squeezing = 1'b 1; Tests: T1 T4 T5  280 281 1/1 if (run_i) begin Tests: T1 T4 T5  282 1/1 st_d = StManualRun_sparse; Tests: T5 T16 T18  283 284 1/1 sw_keccak_run = 1'b 1; Tests: T5 T16 T18  285 1/1 end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin Tests: T1 T4 T5  286 1/1 st_d = StFlush_sparse; Tests: T1 T4 T5  287 288 1/1 keccak_done = done_i; Tests: T1 T4 T5  289 end else begin 290 1/1 st_d = StSqueeze_sparse; Tests: T1 T4 T5  291 end 292 end 293 294 StManualRun_sparse: begin 295 1/1 if (keccak_complete) begin Tests: T5 T16 T18  296 1/1 st_d = StSqueeze_sparse; Tests: T5 T16 T18  297 end else begin 298 1/1 st_d = StManualRun_sparse; Tests: T5 T16 T18  299 end 300 end 301 302 StFlush_sparse: begin 303 1/1 st_d = StIdle_sparse; Tests: T1 T4 T5  304 end 305 306 StTerminalError_sparse: begin 307 //this state is terminal 308 1/1 st_d = StTerminalError_sparse; Tests: T3 T6 T7  309 1/1 sha3_state_error = 1'b 1; Tests: T3 T6 T7  310 end 311 312 default: begin 313 st_d = StTerminalError_sparse; 314 sha3_state_error = 1'b 1; 315 end 316 endcase 317 318 // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC 319 // Unconditionally jump into the terminal error state 320 // if the life cycle controller triggers an escalation. 321 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin Tests: T1 T2 T3  322 1/1 st_d = StTerminalError_sparse; Tests: T3 T6 T7  323 end MISSING_ELSE 324 end 325 326 ////////////// 327 // Datapath // 328 ////////////// 329 330 // State --> Digest output 331 always_comb begin : state_guarded_mux 332 1/1 unique case (mux_sel) Tests: T1 T2 T3  333 1/1 MuxGuard: state_guarded = '{default: '0}; Tests: T1 T2 T3  334 1/1 MuxRelease: state_guarded = state; Tests: T1 T4 T5  335 default: state_guarded = '{default: '0}; // a valid, safe output 336 endcase 337 end 338 339 340 // Error Detecting 341 // ErrSha3SwControl: 342 // info[ 0]: start_i set 343 // info[ 1]: process_i set 344 // info[ 2]: run_i set 345 // info[ 3]: done_i set 346 // - Sw set process_i, run_i, done_i without start_i 347 348 always_comb begin 349 1/1 error_o = '{valid: 1'b0, code: ErrNone, info: '0}; Tests: T1 T2 T3  350 351 1/1 unique case (st) Tests: T1 T2 T3  352 StIdle_sparse: begin 353 1/1 if (process_i || run_i || Tests: T1 T2 T3  354 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 355 1/1 error_o = '{ Tests: T22 T35 T36  356 valid: 1'b 1, 357 code: ErrSha3SwControl, 358 info: 24'({done_i, run_i, process_i, start_i}) 359 }; 360 end MISSING_ELSE 361 end 362 363 StAbsorb_sparse: begin 364 1/1 if (start_i || run_i || prim_mubi_pkg::mubi4_test_true_loose(done_i) Tests: T1 T3 T4  365 || (process_i && processing)) begin 366 1/1 error_o = '{ Tests: T22 T35 T36  367 valid: 1'b 1, 368 code: ErrSha3SwControl, 369 info: 24'({done_i, run_i, process_i, start_i}) 370 }; 371 end MISSING_ELSE 372 end 373 374 StSqueeze_sparse: begin 375 1/1 if (start_i || process_i) begin Tests: T1 T4 T5  376 0/1 ==> error_o = '{ 377 valid: 1'b 1, 378 code: ErrSha3SwControl, 379 info: 24'({done_i, run_i, process_i, start_i}) 380 }; 381 end MISSING_ELSE 382 end 383 384 StManualRun_sparse: begin 385 1/1 if (start_i || process_i || run_i || Tests: T5 T16 T18  386 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 387 1/1 error_o = '{ Tests: T22 T35 T36  388 valid: 1'b 1, 389 code: ErrSha3SwControl, 390 info: 24'({done_i, run_i, process_i, start_i}) 391 }; 392 end MISSING_ELSE 393 end 394 395 StFlush_sparse: begin 396 1/1 if (start_i || process_i || run_i || Tests: T1 T4 T5  397 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 398 0/1 ==> error_o = '{ 399 valid: 1'b 1, 400 code: ErrSha3SwControl, 401 info: 24'({done_i, run_i, process_i, start_i}) 402 }; 403 end MISSING_ELSE

Cond Coverage for Module : sha3
TotalCoveredPercent
Conditions272488.89
Logical272488.89
Non-Logical00
Event00

 LINE       138
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T11,T12
10CoveredT7,T11,T12

 LINE       144
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT7,T11,T12
010CoveredT7,T11,T12
100CoveredT7,T11,T12

 LINE       173
 EXPRESSION ((sha3pad_keccak_run || sw_keccak_run) ? 1'b1 : (keccak_complete ? 1'b0 : keccak_run_req_q))
             ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       173
 SUB-EXPRESSION (sha3pad_keccak_run || sw_keccak_run)
                 ---------1--------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T16,T18
10CoveredT1,T4,T5

 LINE       173
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_run_req_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       178
 EXPRESSION (run_req_o & run_ack_i & ((~keccak_triggered_q)))
             ----1----   ----2----   -----------3-----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110CoveredT1,T4,T5
111CoveredT1,T4,T5

 LINE       179
 EXPRESSION (keccak_run ? 1'b1 : (keccak_complete ? 1'b0 : keccak_triggered_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       179
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_triggered_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       264
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------
-1--2-StatusTests
01CoveredT1,T3,T4
10Not Covered
11CoveredT1,T4,T5

 LINE       375
 EXPRESSION (start_i || process_i)
             ---1---    ----2----
-1--2-StatusTests
00CoveredT1,T4,T5
01Not Covered
10Not Covered

FSM Coverage for Module : sha3
Summary for FSM :: st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 11 10 90.91
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
states   Line No.   Covered   Tests   
StAbsorb_sparse 255 Covered T1,T3,T4
StFlush_sparse 286 Covered T1,T4,T5
StIdle_sparse 259 Covered T1,T2,T3
StManualRun_sparse 282 Covered T5,T16,T18
StSqueeze_sparse 269 Covered T1,T4,T5
StTerminalError_sparse 308 Covered T3,T6,T7


transitions   Line No.   Covered   Tests   
StAbsorb_sparse->StSqueeze_sparse 269 Covered T1,T4,T5
StAbsorb_sparse->StTerminalError_sparse 322 Covered T3,T6,T42
StFlush_sparse->StIdle_sparse 303 Covered T1,T4,T5
StFlush_sparse->StTerminalError_sparse 322 Not Covered
StIdle_sparse->StAbsorb_sparse 255 Covered T1,T3,T4
StIdle_sparse->StTerminalError_sparse 322 Covered T7,T11,T12
StManualRun_sparse->StSqueeze_sparse 296 Covered T5,T16,T18
StManualRun_sparse->StTerminalError_sparse 322 Covered T61
StSqueeze_sparse->StFlush_sparse 286 Covered T1,T4,T5
StSqueeze_sparse->StManualRun_sparse 282 Covered T5,T16,T18
StSqueeze_sparse->StTerminalError_sparse 322 Covered T62



Branch Coverage for Module : sha3
Line No.TotalCoveredPercent
Branches 45 42 93.33
TERNARY 173 3 3 100.00
TERNARY 179 3 3 100.00
IF 184 2 2 100.00
IF 198 2 2 100.00
IF 207 4 4 100.00
IF 227 2 2 100.00
CASE 252 13 13 100.00
IF 321 2 2 100.00
CASE 332 3 2 66.67
CASE 351 11 9 81.82


173 assign keccak_run_req_d = 174 sha3pad_keccak_run || sw_keccak_run ? 1'b 1 : -1- ==> 175 keccak_complete ? 1'b 0 : keccak_run_req_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T5
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


179 assign keccak_triggered_d = 180 keccak_run ? 1'b 1 : -1- ==> 181 keccak_complete ? 1'b 0 : keccak_triggered_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T5
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


184 if (!rst_ni) begin -1- 185 keccak_run_req_q <= 1'b 0; ==> 186 keccak_triggered_q <= 1'b 0; 187 end else begin 188 keccak_run_req_q <= keccak_run_req_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


198 if (!rst_ni) absorbed_o <= prim_mubi_pkg::MuBi4False; -1- ==> 199 else absorbed_o <= absorbed; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


207 if (!rst_ni) processing <= 1'b 0; -1- ==> 208 else if (process_i) processing <= 1'b 1; -2- ==> 209 else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin -3- 210 processing <= 1'b 0; ==> 211 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T4,T5
0 0 0 Covered T1,T2,T3


227 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


252 unique case (st) -1- 253 StIdle_sparse: begin 254 if (start_i) begin -2- 255 st_d = StAbsorb_sparse; ==> 256 257 keccak_start = 1'b 1; 258 end else begin 259 st_d = StIdle_sparse; ==> 260 end 261 end 262 263 StAbsorb_sparse: begin 264 if (process_i && !processing) begin -3- 265 st_d = StAbsorb_sparse; ==> 266 267 keccak_process = 1'b 1; 268 end else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin -4- 269 st_d = StSqueeze_sparse; ==> 270 end else begin 271 st_d = StAbsorb_sparse; ==> 272 end 273 end 274 275 StSqueeze_sparse: begin 276 state_valid = 1'b 1; 277 mux_sel = MuxRelease; // Expose state to register interface 278 279 squeezing = 1'b 1; 280 281 if (run_i) begin -5- 282 st_d = StManualRun_sparse; ==> 283 284 sw_keccak_run = 1'b 1; 285 end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin -6- 286 st_d = StFlush_sparse; ==> 287 288 keccak_done = done_i; 289 end else begin 290 st_d = StSqueeze_sparse; ==> 291 end 292 end 293 294 StManualRun_sparse: begin 295 if (keccak_complete) begin -7- 296 st_d = StSqueeze_sparse; ==> 297 end else begin 298 st_d = StManualRun_sparse; ==> 299 end 300 end 301 302 StFlush_sparse: begin 303 st_d = StIdle_sparse; ==> 304 end 305 306 StTerminalError_sparse: begin 307 //this state is terminal 308 st_d = StTerminalError_sparse; ==> 309 sha3_state_error = 1'b 1; 310 end 311 312 default: begin 313 st_d = StTerminalError_sparse; ==>

Branches:
-1--2--3--4--5--6--7-StatusTests
StIdle_sparse 1 - - - - - Covered T1,T3,T4
StIdle_sparse 0 - - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - - Covered T1,T4,T5
StAbsorb_sparse - 0 1 - - - Covered T1,T4,T5
StAbsorb_sparse - 0 0 - - - Covered T1,T3,T4
StSqueeze_sparse - - - 1 - - Covered T5,T16,T18
StSqueeze_sparse - - - 0 1 - Covered T1,T4,T5
StSqueeze_sparse - - - 0 0 - Covered T1,T4,T5
StManualRun_sparse - - - - - 1 Covered T5,T16,T18
StManualRun_sparse - - - - - 0 Covered T5,T16,T18
StFlush_sparse - - - - - - Covered T1,T4,T5
StTerminalError_sparse - - - - - - Covered T3,T6,T7
default - - - - - - Covered T7,T11,T12


321 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin -1- 322 st_d = StTerminalError_sparse; ==> 323 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T3,T6,T7
0 Covered T1,T2,T3


332 unique case (mux_sel) -1- 333 MuxGuard: state_guarded = '{default: '0}; ==> 334 MuxRelease: state_guarded = state; ==> 335 default: state_guarded = '{default: '0}; // a valid, safe output ==>

Branches:
-1-StatusTests
MuxGuard Covered T1,T2,T3
MuxRelease Covered T1,T4,T5
default Not Covered


351 unique case (st) -1- 352 StIdle_sparse: begin 353 if (process_i || run_i || -2- 354 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 355 error_o = '{ ==> 356 valid: 1'b 1, 357 code: ErrSha3SwControl, 358 info: 24'({done_i, run_i, process_i, start_i}) 359 }; 360 end MISSING_ELSE ==> 361 end 362 363 StAbsorb_sparse: begin 364 if (start_i || run_i || prim_mubi_pkg::mubi4_test_true_loose(done_i) -3- 365 || (process_i && processing)) begin 366 error_o = '{ ==> 367 valid: 1'b 1, 368 code: ErrSha3SwControl, 369 info: 24'({done_i, run_i, process_i, start_i}) 370 }; 371 end MISSING_ELSE ==> 372 end 373 374 StSqueeze_sparse: begin 375 if (start_i || process_i) begin -4- 376 error_o = '{ ==> 377 valid: 1'b 1, 378 code: ErrSha3SwControl, 379 info: 24'({done_i, run_i, process_i, start_i}) 380 }; 381 end MISSING_ELSE ==> 382 end 383 384 StManualRun_sparse: begin 385 if (start_i || process_i || run_i || -5- 386 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 387 error_o = '{ ==> 388 valid: 1'b 1, 389 code: ErrSha3SwControl, 390 info: 24'({done_i, run_i, process_i, start_i}) 391 }; 392 end MISSING_ELSE ==> 393 end 394 395 StFlush_sparse: begin 396 if (start_i || process_i || run_i || -6- 397 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 398 error_o = '{ ==> 399 valid: 1'b 1, 400 code: ErrSha3SwControl, 401 info: 24'({done_i, run_i, process_i, start_i}) 402 }; 403 end MISSING_ELSE ==> 404 end 405 406 default: begin ==>

Branches:
-1--2--3--4--5--6-StatusTests
StIdle_sparse 1 - - - - Covered T22,T35,T36
StIdle_sparse 0 - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - Covered T22,T35,T36
StAbsorb_sparse - 0 - - - Covered T1,T3,T4
StSqueeze_sparse - - 1 - - Not Covered
StSqueeze_sparse - - 0 - - Covered T1,T4,T5
StManualRun_sparse - - - 1 - Covered T22,T35,T36
StManualRun_sparse - - - 0 - Covered T5,T16,T18
StFlush_sparse - - - - 1 Not Covered
StFlush_sparse - - - - 0 Covered T1,T4,T5
default - - - - - Covered T3,T6,T7


Assert Coverage for Module : sha3
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ErrDetection_A 658689546 7919038 0 0
FsmKnown_A 658489119 658354068 0 0
KeccakIdleWhenNoRunHs_A 658689546 21366626 0 0
MuxSelKnown_A 658689546 658548519 0 0
SwRunInSqueezing_a 658689546 120887 0 0
gen_chk_digest_unmasked.StateZeroInvalid_A 658689546 566007201 0 0
u_state_regs_A 658689546 658548519 0 0


ErrDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 7919038 0 0
T7 447197 0 0 0
T20 128896 0 0 0
T22 160569 93669 0 0
T23 292338 0 0 0
T24 432880 0 0 0
T35 0 60633 0 0
T36 0 194611 0 0
T42 3467 0 0 0
T59 0 222634 0 0
T60 0 161570 0 0
T75 9825 0 0 0
T76 2735 0 0 0
T77 364900 0 0 0
T78 98057 0 0 0
T82 0 790256 0 0
T83 0 6327 0 0
T84 0 360872 0 0
T85 0 383401 0 0
T86 0 171071 0 0

FsmKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658489119 658354068 0 0
T1 2547 2481 0 0
T2 1172 1081 0 0
T3 3251 3132 0 0
T4 10781 10704 0 0
T5 28537 28479 0 0
T13 111446 111356 0 0
T14 3069 2980 0 0
T15 7231 7134 0 0
T16 53987 53889 0 0
T17 101745 101647 0 0

KeccakIdleWhenNoRunHs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 21366626 0 0
T1 2547 240 0 0
T2 1172 0 0 0
T3 3251 0 0 0
T4 10781 264 0 0
T5 28537 504 0 0
T13 111446 864 0 0
T14 3069 264 0 0
T15 7231 264 0 0
T16 53987 1440 0 0
T17 101745 4296 0 0
T18 0 4200 0 0
T19 0 648 0 0

MuxSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 658548519 0 0
T1 2547 2481 0 0
T2 1172 1081 0 0
T3 3251 3132 0 0
T4 10781 10704 0 0
T5 28537 28479 0 0
T13 111446 111356 0 0
T14 3069 2980 0 0
T15 7231 7134 0 0
T16 53987 53889 0 0
T17 101745 101647 0 0

SwRunInSqueezing_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 120887 0 0
T5 28537 10 0 0
T13 111446 0 0 0
T14 3069 0 0 0
T15 7231 0 0 0
T16 53987 30 0 0
T17 101745 0 0 0
T18 45441 36 0 0
T19 78388 0 0 0
T22 0 73 0 0
T24 0 138 0 0
T28 0 56 0 0
T32 0 127 0 0
T34 33159 20 0 0
T43 41201 0 0 0
T44 0 58 0 0
T87 0 75 0 0

gen_chk_digest_unmasked.StateZeroInvalid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 566007201 0 0
T1 2547 1954 0 0
T2 1172 1081 0 0
T3 3251 3132 0 0
T4 10781 8341 0 0
T5 28537 18996 0 0
T13 111446 111344 0 0
T14 3069 2385 0 0
T15 7231 5641 0 0
T16 53987 30733 0 0
T17 101745 59549 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 658548519 0 0
T1 2547 2481 0 0
T2 1172 1081 0 0
T3 3251 3132 0 0
T4 10781 10704 0 0
T5 28537 28479 0 0
T13 111446 111356 0 0
T14 3069 2980 0 0
T15 7231 7134 0 0
T16 53987 53889 0 0
T17 101745 101647 0 0

Line Coverage for Instance : tb.dut.u_sha3
Line No.TotalCoveredPercent
TOTAL828097.56
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17911100.00
ALWAYS18455100.00
ALWAYS19833100.00
CONT_ASSIGN20311100.00
ALWAYS20766100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22011100.00
ALWAYS22733100.00
ALWAYS2373838100.00
ALWAYS33233100.00
ALWAYS349121083.33

137 logic round_count_error, msg_count_error; 138 1/1 assign count_error_o = round_count_error | msg_count_error; Tests: T1 T2 T3  139 140 logic sha3_state_error; 141 logic keccak_round_state_error; 142 logic sha3pad_state_error; 143 144 1/1 assign sparse_fsm_error_o = sha3_state_error | keccak_round_state_error | sha3pad_state_error; Tests: T1 T2 T3  145 146 // Keccak rst_storage is asserted unexpectedly 147 logic keccak_storage_rst_error; 148 1/1 assign keccak_storage_rst_error_o = keccak_storage_rst_error; Tests: T1 T2 T3  149 150 ///////////////// 151 // Connections // 152 ///////////////// 153 154 logic keccak_valid; 155 logic [KeccakMsgAddrW-1:0] keccak_addr; 156 logic [MsgWidth-1:0] keccak_data [Share]; 157 logic keccak_ready; 158 159 // Keccak round run signal can be controlled by sha3pad and also by software 160 // after all message feeding is done. it is mainly used for sponge squeezing 161 // operation after absorbing is completed when output length is longer than 162 // the block size. 163 logic keccak_run, sha3pad_keccak_run, sw_keccak_run; 164 logic keccak_run_req_d, keccak_run_req_q; 165 logic keccak_triggered_d, keccak_triggered_q; 166 logic keccak_complete; 167 168 // Announce that we want to run the Keccak core and tell other blocks to go 169 // quiet. Keep holding the REQ until the Keccak core is done with the 170 // processing. The keccak_complete signal is received once the Keccak core 171 // is back in the Idle state and again susceptible to keccak_run. 172 1/1 assign run_req_o = keccak_run_req_d; Tests: T1 T2 T3  173 1/1 assign keccak_run_req_d = Tests: T1 T2 T3  174 sha3pad_keccak_run || sw_keccak_run ? 1'b 1 : 175 keccak_complete ? 1'b 0 : keccak_run_req_q; 176 177 // Trigger the Keccak engine with a single pulse upon receiving the ACK. 178 1/1 assign keccak_run = run_req_o & run_ack_i & ~keccak_triggered_q; Tests: T1 T2 T3  179 1/1 assign keccak_triggered_d = Tests: T1 T2 T3  180 keccak_run ? 1'b 1 : 181 keccak_complete ? 1'b 0 : keccak_triggered_q; 182 183 always_ff @(posedge clk_i or negedge rst_ni) begin 184 1/1 if (!rst_ni) begin Tests: T1 T2 T3  185 1/1 keccak_run_req_q <= 1'b 0; Tests: T1 T2 T3  186 1/1 keccak_triggered_q <= 1'b 0; Tests: T1 T2 T3  187 end else begin 188 1/1 keccak_run_req_q <= keccak_run_req_d; Tests: T1 T2 T3  189 1/1 keccak_triggered_q <= keccak_triggered_d; Tests: T1 T2 T3  190 end 191 end 192 193 // Absorb pulse output : used to generate interrupts 194 // Latch absorbed signal as kmac_keymgr asserts `CmdDone` when it sees 195 // `absorbed` signal. When this signal goes out, the state is still in 196 // `StAbsorb`. Next state is `StSqueeze`. 197 always_ff @(posedge clk_i or negedge rst_ni) begin 198 2/2 if (!rst_ni) absorbed_o <= prim_mubi_pkg::MuBi4False; Tests: T1 T2 T3  | T1 T2 T3  199 1/1 else absorbed_o <= absorbed; Tests: T1 T2 T3  200 end 201 202 // Squeezing output 203 1/1 assign squeezing_o = squeezing; Tests: T1 T2 T3  204 205 // processing 206 always_ff @(posedge clk_i or negedge rst_ni) begin 207 2/2 if (!rst_ni) processing <= 1'b 0; Tests: T1 T2 T3  | T1 T2 T3  208 2/2 else if (process_i) processing <= 1'b 1; Tests: T1 T2 T3  | T1 T4 T5  209 1/1 else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin Tests: T1 T2 T3  210 1/1 processing <= 1'b 0; Tests: T1 T4 T5  211 end MISSING_ELSE 212 end 213 214 1/1 assign block_processed_o = keccak_complete; Tests: T1 T2 T3  215 216 // State connection 217 1/1 assign state_valid_o = state_valid; Tests: T1 T2 T3  218 1/1 assign state_o = state_guarded; Tests: T1 T2 T3  219 220 1/1 assign sha3_fsm_o = sparse2logic(st); Tests: T1 T2 T3  221 222 /////////////////// 223 // State Machine // 224 /////////////////// 225 226 // State Register 227 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse): 227.1 `ifdef SIMULATION 227.2 prim_sparse_fsm_flop #( 227.3 .StateEnumT(sha3_st_sparse_e), 227.4 .Width($bits(sha3_st_sparse_e)), 227.5 .ResetValue($bits(sha3_st_sparse_e)'(StIdle_sparse)), 227.6 .EnableAlertTriggerSVA(1), 227.7 .CustomForceName("st") 227.8 ) u_state_regs ( 227.9 .clk_i ( clk_i ), 227.10 .rst_ni ( rst_ni ), 227.11 .state_i ( st_d ), 227.12 .state_o ( ) 227.13 ); 227.14 always_ff @(posedge clk_i or negedge rst_ni) begin 227.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  227.16 1/1 st <= StIdle_sparse; Tests: T1 T2 T3  227.17 end else begin 227.18 1/1 st <= st_d; Tests: T1 T2 T3  227.19 end 227.20 end 227.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (st === u_state_regs.state_o)) 227.22 else begin 227.23 `ifdef UVM 227.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 227.25 "../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv", 227, "", 1); 227.26 `else 227.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 227.28 `PRIM_STRINGIFY(u_state_regs_A)); 227.29 `endif 227.30 end 227.31 `else 227.32 prim_sparse_fsm_flop #( 227.33 .StateEnumT(sha3_st_sparse_e), 227.34 .Width($bits(sha3_st_sparse_e)), 227.35 .ResetValue($bits(sha3_st_sparse_e)'(StIdle_sparse)), 227.36 .EnableAlertTriggerSVA(1) 227.37 ) u_state_regs ( 227.38 .clk_i ( `PRIM_FLOP_CLK ), 227.39 .rst_ni ( `PRIM_FLOP_RST ), 227.40 .state_i ( st_d ), 227.41 .state_o ( st ) 227.42 ); 227.43 `endif228 229 230 // Next State and Output Logic 231 // Mainly the FSM controls the input signal access 232 // StIdle: only start_i signal is allowed 233 // StAbsorb: only process_i signal is allowed 234 // StSqueeze: only run_i, done_i signal is allowed 235 236 always_comb begin 237 1/1 st_d = st; Tests: T1 T2 T3  238 239 // default output values 240 1/1 keccak_start = 1'b 0; Tests: T1 T2 T3  241 1/1 keccak_process = 1'b 0; Tests: T1 T2 T3  242 1/1 sw_keccak_run = 1'b 0; Tests: T1 T2 T3  243 1/1 keccak_done = prim_mubi_pkg::MuBi4False; Tests: T1 T2 T3  244 245 1/1 squeezing = 1'b 0; Tests: T1 T2 T3  246 247 1/1 state_valid = 1'b 0; Tests: T1 T2 T3  248 1/1 mux_sel = MuxGuard ; Tests: T1 T2 T3  249 250 1/1 sha3_state_error = 1'b 0; Tests: T1 T2 T3  251 252 1/1 unique case (st) Tests: T1 T2 T3  253 StIdle_sparse: begin 254 1/1 if (start_i) begin Tests: T1 T2 T3  255 1/1 st_d = StAbsorb_sparse; Tests: T1 T3 T4  256 257 1/1 keccak_start = 1'b 1; Tests: T1 T3 T4  258 end else begin 259 1/1 st_d = StIdle_sparse; Tests: T1 T2 T3  260 end 261 end 262 263 StAbsorb_sparse: begin 264 1/1 if (process_i && !processing) begin Tests: T1 T3 T4  265 1/1 st_d = StAbsorb_sparse; Tests: T1 T4 T5  266 267 1/1 keccak_process = 1'b 1; Tests: T1 T4 T5  268 1/1 end else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin Tests: T1 T3 T4  269 1/1 st_d = StSqueeze_sparse; Tests: T1 T4 T5  270 end else begin 271 1/1 st_d = StAbsorb_sparse; Tests: T1 T3 T4  272 end 273 end 274 275 StSqueeze_sparse: begin 276 1/1 state_valid = 1'b 1; Tests: T1 T4 T5  277 1/1 mux_sel = MuxRelease; // Expose state to register interface Tests: T1 T4 T5  278 279 1/1 squeezing = 1'b 1; Tests: T1 T4 T5  280 281 1/1 if (run_i) begin Tests: T1 T4 T5  282 1/1 st_d = StManualRun_sparse; Tests: T5 T16 T18  283 284 1/1 sw_keccak_run = 1'b 1; Tests: T5 T16 T18  285 1/1 end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin Tests: T1 T4 T5  286 1/1 st_d = StFlush_sparse; Tests: T1 T4 T5  287 288 1/1 keccak_done = done_i; Tests: T1 T4 T5  289 end else begin 290 1/1 st_d = StSqueeze_sparse; Tests: T1 T4 T5  291 end 292 end 293 294 StManualRun_sparse: begin 295 1/1 if (keccak_complete) begin Tests: T5 T16 T18  296 1/1 st_d = StSqueeze_sparse; Tests: T5 T16 T18  297 end else begin 298 1/1 st_d = StManualRun_sparse; Tests: T5 T16 T18  299 end 300 end 301 302 StFlush_sparse: begin 303 1/1 st_d = StIdle_sparse; Tests: T1 T4 T5  304 end 305 306 StTerminalError_sparse: begin 307 //this state is terminal 308 1/1 st_d = StTerminalError_sparse; Tests: T3 T6 T7  309 1/1 sha3_state_error = 1'b 1; Tests: T3 T6 T7  310 end 311 312 default: begin 313 st_d = StTerminalError_sparse; 314 sha3_state_error = 1'b 1; 315 end 316 endcase 317 318 // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC 319 // Unconditionally jump into the terminal error state 320 // if the life cycle controller triggers an escalation. 321 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin Tests: T1 T2 T3  322 1/1 st_d = StTerminalError_sparse; Tests: T3 T6 T7  323 end MISSING_ELSE 324 end 325 326 ////////////// 327 // Datapath // 328 ////////////// 329 330 // State --> Digest output 331 always_comb begin : state_guarded_mux 332 1/1 unique case (mux_sel) Tests: T1 T2 T3  333 1/1 MuxGuard: state_guarded = '{default: '0}; Tests: T1 T2 T3  334 1/1 MuxRelease: state_guarded = state; Tests: T1 T4 T5  335 default: state_guarded = '{default: '0}; // a valid, safe output 336 endcase 337 end 338 339 340 // Error Detecting 341 // ErrSha3SwControl: 342 // info[ 0]: start_i set 343 // info[ 1]: process_i set 344 // info[ 2]: run_i set 345 // info[ 3]: done_i set 346 // - Sw set process_i, run_i, done_i without start_i 347 348 always_comb begin 349 1/1 error_o = '{valid: 1'b0, code: ErrNone, info: '0}; Tests: T1 T2 T3  350 351 1/1 unique case (st) Tests: T1 T2 T3  352 StIdle_sparse: begin 353 1/1 if (process_i || run_i || Tests: T1 T2 T3  354 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 355 1/1 error_o = '{ Tests: T22 T35 T36  356 valid: 1'b 1, 357 code: ErrSha3SwControl, 358 info: 24'({done_i, run_i, process_i, start_i}) 359 }; 360 end MISSING_ELSE 361 end 362 363 StAbsorb_sparse: begin 364 1/1 if (start_i || run_i || prim_mubi_pkg::mubi4_test_true_loose(done_i) Tests: T1 T3 T4  365 || (process_i && processing)) begin 366 1/1 error_o = '{ Tests: T22 T35 T36  367 valid: 1'b 1, 368 code: ErrSha3SwControl, 369 info: 24'({done_i, run_i, process_i, start_i}) 370 }; 371 end MISSING_ELSE 372 end 373 374 StSqueeze_sparse: begin 375 1/1 if (start_i || process_i) begin Tests: T1 T4 T5  376 0/1 ==> error_o = '{ 377 valid: 1'b 1, 378 code: ErrSha3SwControl, 379 info: 24'({done_i, run_i, process_i, start_i}) 380 }; 381 end MISSING_ELSE 382 end 383 384 StManualRun_sparse: begin 385 1/1 if (start_i || process_i || run_i || Tests: T5 T16 T18  386 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 387 1/1 error_o = '{ Tests: T22 T35 T36  388 valid: 1'b 1, 389 code: ErrSha3SwControl, 390 info: 24'({done_i, run_i, process_i, start_i}) 391 }; 392 end MISSING_ELSE 393 end 394 395 StFlush_sparse: begin 396 1/1 if (start_i || process_i || run_i || Tests: T1 T4 T5  397 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 398 0/1 ==> error_o = '{ 399 valid: 1'b 1, 400 code: ErrSha3SwControl, 401 info: 24'({done_i, run_i, process_i, start_i}) 402 }; 403 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sha3
TotalCoveredPercent
Conditions272488.89
Logical272488.89
Non-Logical00
Event00

 LINE       138
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T11,T12
10CoveredT7,T11,T12

 LINE       144
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT7,T11,T12
010CoveredT7,T11,T12
100CoveredT7,T11,T12

 LINE       173
 EXPRESSION ((sha3pad_keccak_run || sw_keccak_run) ? 1'b1 : (keccak_complete ? 1'b0 : keccak_run_req_q))
             ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       173
 SUB-EXPRESSION (sha3pad_keccak_run || sw_keccak_run)
                 ---------1--------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T16,T18
10CoveredT1,T4,T5

 LINE       173
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_run_req_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       178
 EXPRESSION (run_req_o & run_ack_i & ((~keccak_triggered_q)))
             ----1----   ----2----   -----------3-----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110CoveredT1,T4,T5
111CoveredT1,T4,T5

 LINE       179
 EXPRESSION (keccak_run ? 1'b1 : (keccak_complete ? 1'b0 : keccak_triggered_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       179
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_triggered_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       264
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------
-1--2-StatusTests
01CoveredT1,T3,T4
10Not Covered
11CoveredT1,T4,T5

 LINE       375
 EXPRESSION (start_i || process_i)
             ---1---    ----2----
-1--2-StatusTests
00CoveredT1,T4,T5
01Not Covered
10Not Covered

FSM Coverage for Instance : tb.dut.u_sha3
Summary for FSM :: st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 9 9 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
states   Line No.   Covered   Tests   
StAbsorb_sparse 255 Covered T1,T3,T4
StFlush_sparse 286 Covered T1,T4,T5
StIdle_sparse 259 Covered T1,T2,T3
StManualRun_sparse 282 Covered T5,T16,T18
StSqueeze_sparse 269 Covered T1,T4,T5
StTerminalError_sparse 308 Covered T3,T6,T7


transitions   Line No.   Covered   Tests   Exclude Annotation   
StAbsorb_sparse->StSqueeze_sparse 269 Covered T1,T4,T5
StAbsorb_sparse->StTerminalError_sparse 322 Covered T3,T6,T42
StFlush_sparse->StIdle_sparse 303 Covered T1,T4,T5
StFlush_sparse->StTerminalError_sparse 322 Excluded [LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StIdle_sparse->StAbsorb_sparse 255 Covered T1,T3,T4
StIdle_sparse->StTerminalError_sparse 322 Covered T7,T11,T12
StManualRun_sparse->StSqueeze_sparse 296 Covered T5,T16,T18
StManualRun_sparse->StTerminalError_sparse 322 Excluded T61 [LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StSqueeze_sparse->StFlush_sparse 286 Covered T1,T4,T5
StSqueeze_sparse->StManualRun_sparse 282 Covered T5,T16,T18
StSqueeze_sparse->StTerminalError_sparse 322 Covered T62



Branch Coverage for Instance : tb.dut.u_sha3
Line No.TotalCoveredPercent
Branches 45 42 93.33
TERNARY 173 3 3 100.00
TERNARY 179 3 3 100.00
IF 184 2 2 100.00
IF 198 2 2 100.00
IF 207 4 4 100.00
IF 227 2 2 100.00
CASE 252 13 13 100.00
IF 321 2 2 100.00
CASE 332 3 2 66.67
CASE 351 11 9 81.82


173 assign keccak_run_req_d = 174 sha3pad_keccak_run || sw_keccak_run ? 1'b 1 : -1- ==> 175 keccak_complete ? 1'b 0 : keccak_run_req_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T5
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


179 assign keccak_triggered_d = 180 keccak_run ? 1'b 1 : -1- ==> 181 keccak_complete ? 1'b 0 : keccak_triggered_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T5
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


184 if (!rst_ni) begin -1- 185 keccak_run_req_q <= 1'b 0; ==> 186 keccak_triggered_q <= 1'b 0; 187 end else begin 188 keccak_run_req_q <= keccak_run_req_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


198 if (!rst_ni) absorbed_o <= prim_mubi_pkg::MuBi4False; -1- ==> 199 else absorbed_o <= absorbed; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


207 if (!rst_ni) processing <= 1'b 0; -1- ==> 208 else if (process_i) processing <= 1'b 1; -2- ==> 209 else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin -3- 210 processing <= 1'b 0; ==> 211 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T4,T5
0 0 0 Covered T1,T2,T3


227 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


252 unique case (st) -1- 253 StIdle_sparse: begin 254 if (start_i) begin -2- 255 st_d = StAbsorb_sparse; ==> 256 257 keccak_start = 1'b 1; 258 end else begin 259 st_d = StIdle_sparse; ==> 260 end 261 end 262 263 StAbsorb_sparse: begin 264 if (process_i && !processing) begin -3- 265 st_d = StAbsorb_sparse; ==> 266 267 keccak_process = 1'b 1; 268 end else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin -4- 269 st_d = StSqueeze_sparse; ==> 270 end else begin 271 st_d = StAbsorb_sparse; ==> 272 end 273 end 274 275 StSqueeze_sparse: begin 276 state_valid = 1'b 1; 277 mux_sel = MuxRelease; // Expose state to register interface 278 279 squeezing = 1'b 1; 280 281 if (run_i) begin -5- 282 st_d = StManualRun_sparse; ==> 283 284 sw_keccak_run = 1'b 1; 285 end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin -6- 286 st_d = StFlush_sparse; ==> 287 288 keccak_done = done_i; 289 end else begin 290 st_d = StSqueeze_sparse; ==> 291 end 292 end 293 294 StManualRun_sparse: begin 295 if (keccak_complete) begin -7- 296 st_d = StSqueeze_sparse; ==> 297 end else begin 298 st_d = StManualRun_sparse; ==> 299 end 300 end 301 302 StFlush_sparse: begin 303 st_d = StIdle_sparse; ==> 304 end 305 306 StTerminalError_sparse: begin 307 //this state is terminal 308 st_d = StTerminalError_sparse; ==> 309 sha3_state_error = 1'b 1; 310 end 311 312 default: begin 313 st_d = StTerminalError_sparse; ==>

Branches:
-1--2--3--4--5--6--7-StatusTests
StIdle_sparse 1 - - - - - Covered T1,T3,T4
StIdle_sparse 0 - - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - - Covered T1,T4,T5
StAbsorb_sparse - 0 1 - - - Covered T1,T4,T5
StAbsorb_sparse - 0 0 - - - Covered T1,T3,T4
StSqueeze_sparse - - - 1 - - Covered T5,T16,T18
StSqueeze_sparse - - - 0 1 - Covered T1,T4,T5
StSqueeze_sparse - - - 0 0 - Covered T1,T4,T5
StManualRun_sparse - - - - - 1 Covered T5,T16,T18
StManualRun_sparse - - - - - 0 Covered T5,T16,T18
StFlush_sparse - - - - - - Covered T1,T4,T5
StTerminalError_sparse - - - - - - Covered T3,T6,T7
default - - - - - - Covered T7,T11,T12


321 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin -1- 322 st_d = StTerminalError_sparse; ==> 323 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T3,T6,T7
0 Covered T1,T2,T3


332 unique case (mux_sel) -1- 333 MuxGuard: state_guarded = '{default: '0}; ==> 334 MuxRelease: state_guarded = state; ==> 335 default: state_guarded = '{default: '0}; // a valid, safe output ==>

Branches:
-1-StatusTests
MuxGuard Covered T1,T2,T3
MuxRelease Covered T1,T4,T5
default Not Covered


351 unique case (st) -1- 352 StIdle_sparse: begin 353 if (process_i || run_i || -2- 354 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 355 error_o = '{ ==> 356 valid: 1'b 1, 357 code: ErrSha3SwControl, 358 info: 24'({done_i, run_i, process_i, start_i}) 359 }; 360 end MISSING_ELSE ==> 361 end 362 363 StAbsorb_sparse: begin 364 if (start_i || run_i || prim_mubi_pkg::mubi4_test_true_loose(done_i) -3- 365 || (process_i && processing)) begin 366 error_o = '{ ==> 367 valid: 1'b 1, 368 code: ErrSha3SwControl, 369 info: 24'({done_i, run_i, process_i, start_i}) 370 }; 371 end MISSING_ELSE ==> 372 end 373 374 StSqueeze_sparse: begin 375 if (start_i || process_i) begin -4- 376 error_o = '{ ==> 377 valid: 1'b 1, 378 code: ErrSha3SwControl, 379 info: 24'({done_i, run_i, process_i, start_i}) 380 }; 381 end MISSING_ELSE ==> 382 end 383 384 StManualRun_sparse: begin 385 if (start_i || process_i || run_i || -5- 386 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 387 error_o = '{ ==> 388 valid: 1'b 1, 389 code: ErrSha3SwControl, 390 info: 24'({done_i, run_i, process_i, start_i}) 391 }; 392 end MISSING_ELSE ==> 393 end 394 395 StFlush_sparse: begin 396 if (start_i || process_i || run_i || -6- 397 prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin 398 error_o = '{ ==> 399 valid: 1'b 1, 400 code: ErrSha3SwControl, 401 info: 24'({done_i, run_i, process_i, start_i}) 402 }; 403 end MISSING_ELSE ==> 404 end 405 406 default: begin ==>

Branches:
-1--2--3--4--5--6-StatusTests
StIdle_sparse 1 - - - - Covered T22,T35,T36
StIdle_sparse 0 - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - Covered T22,T35,T36
StAbsorb_sparse - 0 - - - Covered T1,T3,T4
StSqueeze_sparse - - 1 - - Not Covered
StSqueeze_sparse - - 0 - - Covered T1,T4,T5
StManualRun_sparse - - - 1 - Covered T22,T35,T36
StManualRun_sparse - - - 0 - Covered T5,T16,T18
StFlush_sparse - - - - 1 Not Covered
StFlush_sparse - - - - 0 Covered T1,T4,T5
default - - - - - Covered T3,T6,T7


Assert Coverage for Instance : tb.dut.u_sha3
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ErrDetection_A 658689546 7919038 0 0
FsmKnown_A 658489119 658354068 0 0
KeccakIdleWhenNoRunHs_A 658689546 21366626 0 0
MuxSelKnown_A 658689546 658548519 0 0
SwRunInSqueezing_a 658689546 120887 0 0
gen_chk_digest_unmasked.StateZeroInvalid_A 658689546 566007201 0 0
u_state_regs_A 658689546 658548519 0 0


ErrDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 7919038 0 0
T7 447197 0 0 0
T20 128896 0 0 0
T22 160569 93669 0 0
T23 292338 0 0 0
T24 432880 0 0 0
T35 0 60633 0 0
T36 0 194611 0 0
T42 3467 0 0 0
T59 0 222634 0 0
T60 0 161570 0 0
T75 9825 0 0 0
T76 2735 0 0 0
T77 364900 0 0 0
T78 98057 0 0 0
T82 0 790256 0 0
T83 0 6327 0 0
T84 0 360872 0 0
T85 0 383401 0 0
T86 0 171071 0 0

FsmKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658489119 658354068 0 0
T1 2547 2481 0 0
T2 1172 1081 0 0
T3 3251 3132 0 0
T4 10781 10704 0 0
T5 28537 28479 0 0
T13 111446 111356 0 0
T14 3069 2980 0 0
T15 7231 7134 0 0
T16 53987 53889 0 0
T17 101745 101647 0 0

KeccakIdleWhenNoRunHs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 21366626 0 0
T1 2547 240 0 0
T2 1172 0 0 0
T3 3251 0 0 0
T4 10781 264 0 0
T5 28537 504 0 0
T13 111446 864 0 0
T14 3069 264 0 0
T15 7231 264 0 0
T16 53987 1440 0 0
T17 101745 4296 0 0
T18 0 4200 0 0
T19 0 648 0 0

MuxSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 658548519 0 0
T1 2547 2481 0 0
T2 1172 1081 0 0
T3 3251 3132 0 0
T4 10781 10704 0 0
T5 28537 28479 0 0
T13 111446 111356 0 0
T14 3069 2980 0 0
T15 7231 7134 0 0
T16 53987 53889 0 0
T17 101745 101647 0 0

SwRunInSqueezing_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 120887 0 0
T5 28537 10 0 0
T13 111446 0 0 0
T14 3069 0 0 0
T15 7231 0 0 0
T16 53987 30 0 0
T17 101745 0 0 0
T18 45441 36 0 0
T19 78388 0 0 0
T22 0 73 0 0
T24 0 138 0 0
T28 0 56 0 0
T32 0 127 0 0
T34 33159 20 0 0
T43 41201 0 0 0
T44 0 58 0 0
T87 0 75 0 0

gen_chk_digest_unmasked.StateZeroInvalid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 566007201 0 0
T1 2547 1954 0 0
T2 1172 1081 0 0
T3 3251 3132 0 0
T4 10781 8341 0 0
T5 28537 18996 0 0
T13 111446 111344 0 0
T14 3069 2385 0 0
T15 7231 5641 0 0
T16 53987 30733 0 0
T17 101745 59549 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658689546 658548519 0 0
T1 2547 2481 0 0
T2 1172 1081 0 0
T3 3251 3132 0 0
T4 10781 10704 0 0
T5 28537 28479 0 0
T13 111446 111356 0 0
T14 3069 2980 0 0
T15 7231 7134 0 0
T16 53987 53889 0 0
T17 101745 101647 0 0