Module Definition
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Module : kmac_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.kmac_csr_assert 100.00 100.00



Module Instance : tb.dut.kmac_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : kmac_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 660238794 4440 0 0
entropy_period_rd_A 660238794 2319 0 0
intr_enable_rd_A 660238794 3023 0 0
prefix_0_rd_A 660238794 2361 0 0
prefix_10_rd_A 660238794 2385 0 0
prefix_1_rd_A 660238794 2466 0 0
prefix_2_rd_A 660238794 2436 0 0
prefix_3_rd_A 660238794 2466 0 0
prefix_4_rd_A 660238794 2392 0 0
prefix_5_rd_A 660238794 2367 0 0
prefix_6_rd_A 660238794 2361 0 0
prefix_7_rd_A 660238794 2449 0 0
prefix_8_rd_A 660238794 2384 0 0
prefix_9_rd_A 660238794 2462 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 4440 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 1421 0 0
T57 0 198 0 0
T58 0 1 0 0
T59 321466 0 0 0
T102 0 1 0 0
T104 0 2 0 0
T105 0 2 0 0
T107 0 204 0 0
T111 0 63 0 0
T117 0 6 0 0
T119 0 4 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0

entropy_period_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2319 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 16 0 0
T59 321466 0 0 0
T100 0 22 0 0
T102 0 15 0 0
T105 0 55 0 0
T109 0 6 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 6 0 0
T142 0 26 0 0
T143 0 9 0 0
T144 0 4 0 0
T145 0 218 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 3023 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 18 0 0
T59 321466 0 0 0
T100 0 24 0 0
T102 0 14 0 0
T105 0 95 0 0
T109 0 10 0 0
T110 0 3 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 3 0 0
T142 0 19 0 0
T143 0 2 0 0
T146 0 9 0 0

prefix_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2361 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 17 0 0
T59 321466 0 0 0
T100 0 23 0 0
T102 0 15 0 0
T105 0 33 0 0
T109 0 9 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 1 0 0
T142 0 39 0 0
T143 0 2 0 0
T144 0 2 0 0
T146 0 2 0 0

prefix_10_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2385 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 24 0 0
T59 321466 0 0 0
T100 0 41 0 0
T102 0 6 0 0
T105 0 38 0 0
T109 0 1 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 2 0 0
T142 0 29 0 0
T143 0 7 0 0
T144 0 4 0 0
T146 0 8 0 0

prefix_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2466 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 29 0 0
T59 321466 0 0 0
T100 0 23 0 0
T102 0 3 0 0
T105 0 43 0 0
T109 0 4 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 6 0 0
T142 0 23 0 0
T143 0 3 0 0
T144 0 12 0 0
T146 0 3 0 0

prefix_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2436 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 30 0 0
T59 321466 0 0 0
T100 0 27 0 0
T102 0 8 0 0
T105 0 39 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 4 0 0
T142 0 18 0 0
T143 0 8 0 0
T144 0 6 0 0
T145 0 489 0 0
T146 0 7 0 0

prefix_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2466 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 23 0 0
T59 321466 0 0 0
T100 0 17 0 0
T102 0 6 0 0
T105 0 29 0 0
T109 0 14 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T142 0 32 0 0
T143 0 6 0 0
T144 0 5 0 0
T145 0 477 0 0
T146 0 4 0 0

prefix_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2392 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 15 0 0
T59 321466 0 0 0
T100 0 18 0 0
T102 0 4 0 0
T105 0 29 0 0
T109 0 12 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 8 0 0
T142 0 29 0 0
T143 0 7 0 0
T144 0 11 0 0
T145 0 466 0 0

prefix_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2367 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 17 0 0
T59 321466 0 0 0
T100 0 44 0 0
T102 0 8 0 0
T105 0 41 0 0
T109 0 5 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 4 0 0
T142 0 23 0 0
T143 0 3 0 0
T144 0 3 0 0
T146 0 3 0 0

prefix_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2361 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 22 0 0
T59 321466 0 0 0
T100 0 29 0 0
T102 0 6 0 0
T105 0 40 0 0
T109 0 9 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T142 0 22 0 0
T143 0 3 0 0
T144 0 6 0 0
T145 0 451 0 0
T146 0 1 0 0

prefix_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2449 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 14 0 0
T59 321466 0 0 0
T100 0 35 0 0
T102 0 11 0 0
T105 0 31 0 0
T109 0 14 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 1 0 0
T142 0 53 0 0
T144 0 9 0 0
T145 0 439 0 0
T146 0 6 0 0

prefix_8_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2384 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 30 0 0
T59 321466 0 0 0
T100 0 44 0 0
T102 0 4 0 0
T105 0 32 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 6 0 0
T142 0 23 0 0
T143 0 6 0 0
T144 0 10 0 0
T145 0 478 0 0
T146 0 6 0 0

prefix_9_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 660238794 2462 0 0
T31 24493 0 0 0
T35 279195 0 0 0
T36 323737 0 0 0
T53 270302 31 0 0
T59 321466 0 0 0
T100 0 25 0 0
T102 0 4 0 0
T105 0 24 0 0
T109 0 7 0 0
T120 1327 0 0 0
T121 667344 0 0 0
T122 1524 0 0 0
T123 104529 0 0 0
T124 347643 0 0 0
T141 0 8 0 0
T142 0 21 0 0
T143 0 6 0 0
T144 0 8 0 0
T146 0 5 0 0

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