Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40156384	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

50167924

1

T1

416

T2

553

T3

165

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48846026	1			T1	335		T2	513		T3	94
values[0x0]	20107858	1			T1	142		T2	225		T3	45
values[0x1]	21370424	1			T1	171		T2	244		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31175745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

59148563

1

T1

473

T2

654

T3

168

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	300127	1			T1	2		T4	5		T12	11
valid_sources[0x01]	297715	1			T1	1		T4	20		T12	15
valid_sources[0x02]	291451	1			T1	1		T4	1		T12	11
valid_sources[0x03]	295820	1			T1	2		T4	18		T12	17
valid_sources[0x04]	294923	1			T1	5		T4	1		T12	7
valid_sources[0x05]	294819	1			T1	3		T4	15		T12	17
valid_sources[0x06]	296383	1			T1	4		T12	8		T13	1
valid_sources[0x07]	361216	1			T1	2		T4	21		T12	17
valid_sources[0x08]	293316	1			T1	1		T3	1		T4	12
valid_sources[0x09]	294383	1			T1	5		T4	5		T12	12
valid_sources[0x0a]	295717	1			T1	5		T3	4		T4	50
valid_sources[0x0b]	294941	1			T1	2		T4	9		T12	9
valid_sources[0x0c]	424252	1			T1	3		T4	4		T12	11
valid_sources[0x0d]	423823	1			T1	5		T3	1		T12	20
valid_sources[0x0e]	330181	1			T1	3		T3	1		T12	8
valid_sources[0x0f]	293751	1			T1	2		T4	48		T12	21
valid_sources[0x10]	293737	1			T1	1		T3	2		T12	12
valid_sources[0x11]	290779	1			T3	2		T4	30		T12	15
valid_sources[0x12]	294266	1			T1	5		T4	9		T12	19
valid_sources[0x13]	305972	1			T1	3		T4	30		T12	22
valid_sources[0x14]	298107	1			T1	3		T4	8		T12	9
valid_sources[0x15]	453043	1			T1	1		T4	13		T12	7
valid_sources[0x16]	298087	1			T1	2		T4	11		T12	13
valid_sources[0x17]	927235	1			T1	6		T12	15		T5	1
valid_sources[0x18]	294672	1			T1	4		T12	8		T13	1
valid_sources[0x19]	298829	1			T1	2		T4	1		T12	13
valid_sources[0x1a]	292885	1			T4	8		T12	13		T17	33
valid_sources[0x1b]	869135	1			T1	6		T4	21		T12	13
valid_sources[0x1c]	308834	1			T1	1		T3	3		T4	2
valid_sources[0x1d]	464935	1			T1	1		T4	28		T12	13
valid_sources[0x1e]	296794	1			T1	3		T4	24		T12	15
valid_sources[0x1f]	294895	1			T1	2		T4	49		T12	12
valid_sources[0x20]	313494	1			T1	5		T4	2		T12	16
valid_sources[0x21]	1318793	1			T1	3		T12	13		T13	10
valid_sources[0x22]	293483	1			T1	4		T3	2		T12	15
valid_sources[0x23]	294675	1			T1	2		T12	9		T5	3
valid_sources[0x24]	705790	1			T1	1		T4	26		T12	12
valid_sources[0x25]	298098	1			T1	5		T4	8		T12	19
valid_sources[0x26]	294564	1			T1	4		T4	19		T12	14
valid_sources[0x27]	290764	1			T1	4		T4	3		T12	12
valid_sources[0x28]	296111	1			T1	3		T4	34		T12	25
valid_sources[0x29]	295620	1			T1	6		T3	2		T4	26
valid_sources[0x2a]	293688	1			T1	5		T4	1		T12	10
valid_sources[0x2b]	295141	1			T3	3		T4	1		T12	4
valid_sources[0x2c]	351518	1			T3	1		T4	3		T12	4
valid_sources[0x2d]	311038	1			T1	3		T4	16		T12	9
valid_sources[0x2e]	295818	1			T1	4		T4	5		T12	9
valid_sources[0x2f]	336149	1			T1	1		T3	2		T4	6
valid_sources[0x30]	297462	1			T1	4		T3	4		T4	26
valid_sources[0x31]	1305562	1			T1	4		T4	27		T12	11
valid_sources[0x32]	307895	1			T1	2		T3	2		T4	21
valid_sources[0x33]	324083	1			T1	3		T4	1		T12	6
valid_sources[0x34]	293438	1			T1	1		T12	6		T13	5
valid_sources[0x35]	295598	1			T1	3		T3	3		T4	10
valid_sources[0x36]	291264	1			T1	3		T3	4		T4	13
valid_sources[0x37]	667102	1			T4	47		T12	21		T14	19
valid_sources[0x38]	295419	1			T1	4		T4	8		T12	5
valid_sources[0x39]	294563	1			T1	1		T3	1		T4	3
valid_sources[0x3a]	328089	1			T1	5		T12	4		T14	6
valid_sources[0x3b]	298215	1			T1	3		T4	2		T12	11
valid_sources[0x3c]	295083	1			T1	1		T3	4		T4	41
valid_sources[0x3d]	313641	1			T1	5		T3	3		T4	4
valid_sources[0x3e]	296194	1			T1	4		T4	1		T12	7
valid_sources[0x3f]	298774	1			T1	2		T3	3		T4	4
valid_sources[0x40]	296414	1			T1	2		T3	5		T4	7
valid_sources[0x41]	294038	1			T1	2		T3	1		T4	8
valid_sources[0x42]	299003	1			T1	6		T2	982		T4	3
valid_sources[0x43]	292870	1			T1	1		T4	13		T12	10
valid_sources[0x44]	296739	1			T1	2		T4	10		T12	16
valid_sources[0x45]	291066	1			T1	1		T3	1		T4	22
valid_sources[0x46]	297244	1			T1	2		T4	3		T12	14
valid_sources[0x47]	310151	1			T1	1		T4	11		T12	12
valid_sources[0x48]	477475	1			T1	4		T4	19		T12	14
valid_sources[0x49]	296205	1			T1	1		T3	1		T4	28
valid_sources[0x4a]	292593	1			T1	3		T4	31		T12	8
valid_sources[0x4b]	295959	1			T1	3		T4	11		T12	16
valid_sources[0x4c]	328991	1			T1	3		T4	3		T12	8
valid_sources[0x4d]	293744	1			T1	2		T4	4		T12	14
valid_sources[0x4e]	484834	1			T1	2		T4	11		T12	22
valid_sources[0x4f]	294291	1			T1	1		T3	1		T4	4
valid_sources[0x50]	764013	1			T1	3		T4	13		T12	18
valid_sources[0x51]	296264	1			T1	3		T4	9		T12	15
valid_sources[0x52]	408621	1			T1	2		T4	3		T12	26
valid_sources[0x53]	365117	1			T1	4		T4	9		T12	13
valid_sources[0x54]	292510	1			T1	2		T3	3		T4	13
valid_sources[0x55]	324384	1			T1	4		T3	4		T4	12
valid_sources[0x56]	454362	1			T1	5		T12	24		T15	8
valid_sources[0x57]	667945	1			T1	3		T3	5		T4	10
valid_sources[0x58]	294653	1			T1	1		T3	1		T4	14
valid_sources[0x59]	292398	1			T1	1		T4	31		T12	17
valid_sources[0x5a]	295095	1			T1	4		T4	1		T12	14
valid_sources[0x5b]	376882	1			T1	2		T4	1		T12	5
valid_sources[0x5c]	335952	1			T1	1		T4	29		T12	15
valid_sources[0x5d]	292281	1			T1	2		T3	3		T12	21
valid_sources[0x5e]	300056	1			T1	1		T4	19		T12	11
valid_sources[0x5f]	296971	1			T1	5		T4	1		T12	24
valid_sources[0x60]	295651	1			T1	2		T4	22		T12	24
valid_sources[0x61]	300722	1			T1	5		T4	29		T12	22
valid_sources[0x62]	295372	1			T1	1		T4	44		T12	11
valid_sources[0x63]	298574	1			T3	2		T4	7		T12	5
valid_sources[0x64]	425370	1			T1	2		T3	4		T19	2
valid_sources[0x65]	295653	1			T1	1		T4	1		T12	13
valid_sources[0x66]	293341	1			T1	4		T4	6		T12	8
valid_sources[0x67]	310676	1			T1	4		T4	14		T12	7
valid_sources[0x68]	432599	1			T1	3		T4	4		T12	21
valid_sources[0x69]	330607	1			T1	4		T3	2		T4	6
valid_sources[0x6a]	293395	1			T1	1		T4	3		T12	8
valid_sources[0x6b]	375125	1			T1	1		T4	10		T12	18
valid_sources[0x6c]	350557	1			T1	1		T3	4		T4	1
valid_sources[0x6d]	292618	1			T1	1		T4	9		T12	19
valid_sources[0x6e]	295479	1			T1	1		T12	13		T13	1
valid_sources[0x6f]	294922	1			T1	3		T4	6		T12	15
valid_sources[0x70]	297451	1			T1	4		T4	27		T12	14
valid_sources[0x71]	300143	1			T1	3		T4	2		T12	18
valid_sources[0x72]	294860	1			T1	4		T3	8		T4	6
valid_sources[0x73]	330406	1			T1	4		T4	7		T12	13
valid_sources[0x74]	296084	1			T1	2		T3	2		T4	4
valid_sources[0x75]	293251	1			T1	3		T3	4		T12	21
valid_sources[0x76]	337391	1			T1	2		T4	17		T12	12
valid_sources[0x77]	600706	1			T1	2		T4	13		T12	15
valid_sources[0x78]	398746	1			T3	1		T4	9		T12	9
valid_sources[0x79]	293712	1			T1	3		T4	19		T12	10
valid_sources[0x7a]	292230	1			T1	2		T4	1		T12	19
valid_sources[0x7b]	294681	1			T1	3		T4	7		T12	18
valid_sources[0x7c]	297154	1			T1	3		T12	10		T15	5
valid_sources[0x7d]	294482	1			T1	5		T4	18		T12	21
valid_sources[0x7e]	294125	1			T1	1		T19	4		T4	3
valid_sources[0x7f]	305473	1			T4	20		T12	12		T14	4
valid_sources[0x80]	294902	1			T1	1		T4	10		T12	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24103008

1

T1

214

T2

281

T3

88

values[0x0]

all_enables

biggest_size

13674063

1

T1

99

T2

144

T3

42

values[0x1]

all_enables

biggest_size

12390853

1

T1

103

T2

128

T3

35