Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

40211590

1

T1

232

T2

429

T3

15

full_word

50171309

1

T1

416

T2

553

T3

165

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	90382589	1			T1	648		T2	982		T3	180
auto[TlIntgErrCmd]	90	1			T124	6		T125	7		T126	3
auto[TlIntgErrData]	105	1			T124	6		T125	5		T126	9
auto[TlIntgErrBoth]	115	1			T124	8		T125	8		T126	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48858229

1

T1

335

T2

513

T3

94

auto[1]

41524670

1

T1

313

T2

469

T3

86

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24754150	1			T1	121		T2	232		T3	6
auto[TlIntgErrNone]	partial	auto[1]	15457167	1			T1	111		T2	197		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	24103932	1			T1	214		T2	281		T3	88
auto[TlIntgErrNone]	full_word	auto[1]	26067340	1			T1	202		T2	272		T3	77
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T124	3		T125	1		T139	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T124	2		T125	6		T126	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T124	1		T139	1		T181	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T184	1		T185	2		T183	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T124	3		T125	2		T126	4
auto[TlIntgErrData]	partial	auto[1]	46	1			T124	3		T125	3		T126	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T186	1		T187	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T188	1		T187	1		T189	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T124	2		T125	4		T126	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T124	4		T125	4		T126	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T126	1		T185	1		T186	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T124	2		T126	1		T139	1