Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T2 T3
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T2 T3
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T3
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
46095439 |
0 |
0 |
| T1 |
2239 |
71 |
0 |
0 |
| T2 |
8037 |
148 |
0 |
0 |
| T3 |
3074 |
9 |
0 |
0 |
| T4 |
47171 |
241 |
0 |
0 |
| T5 |
0 |
19 |
0 |
0 |
| T12 |
28122 |
113 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
252 |
0 |
0 |
| T15 |
5207 |
57 |
0 |
0 |
| T16 |
2780 |
123 |
0 |
0 |
| T17 |
0 |
995 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
46095439 |
0 |
0 |
| T1 |
2239 |
71 |
0 |
0 |
| T2 |
8037 |
148 |
0 |
0 |
| T3 |
3074 |
9 |
0 |
0 |
| T4 |
47171 |
241 |
0 |
0 |
| T5 |
0 |
19 |
0 |
0 |
| T12 |
28122 |
113 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
252 |
0 |
0 |
| T15 |
5207 |
57 |
0 |
0 |
| T16 |
2780 |
123 |
0 |
0 |
| T17 |
0 |
995 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 11 | 78.57 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 0 | 0 | |
| CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
| ALWAYS | 111 | 2 | 1 | 50.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 unreachable assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 0/1 ==> storage[0] <= wdata_i;
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 0/1 ==> assign rdata_int = storage_rdata;
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Total | Covered | Percent |
|---|
| Conditions | 13 | 5 | 38.46 |
| Logical | 13 | 5 | 38.46 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
5 |
71.43 |
| TERNARY |
138 |
2 |
1 |
50.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
1 |
50.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Not Covered |
|
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 13 | 12 | 92.31 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 0 | 0 | |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
| ALWAYS | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 unreachable assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 unreachable storage[0] <= wdata_i;
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Total | Covered | Percent |
|---|
| Conditions | 17 | 8 | 47.06 |
| Logical | 17 | 8 | 47.06 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Unreachable | |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Unreachable | |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
6 |
85.71 |
| TERNARY |
130 |
1 |
1 |
100.00 |
| TERNARY |
138 |
2 |
1 |
50.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
1 |
1 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==> (Unreachable)
==>
Branches:
| -1- | Status | Tests |
| 1 |
Unreachable |
|
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Not Covered |
|
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==> (Unreachable)
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Unreachable |
|
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T4
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Total | Covered | Percent |
|---|
| Conditions | 24 | 21 | 87.50 |
| Logical | 24 | 21 | 87.50 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T21,T39,T52 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T21,T39,T52 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T4 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T16 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (72'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T4 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
17527861 |
0 |
0 |
| T1 |
2239 |
238 |
0 |
0 |
| T2 |
8037 |
79 |
0 |
0 |
| T3 |
3074 |
0 |
0 |
0 |
| T4 |
47171 |
718 |
0 |
0 |
| T5 |
0 |
73 |
0 |
0 |
| T12 |
28122 |
247 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
35 |
0 |
0 |
| T15 |
5207 |
66 |
0 |
0 |
| T16 |
2780 |
225 |
0 |
0 |
| T17 |
0 |
908 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
| T80 |
0 |
360 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
17527861 |
0 |
0 |
| T1 |
2239 |
238 |
0 |
0 |
| T2 |
8037 |
79 |
0 |
0 |
| T3 |
3074 |
0 |
0 |
0 |
| T4 |
47171 |
718 |
0 |
0 |
| T5 |
0 |
73 |
0 |
0 |
| T12 |
28122 |
247 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
35 |
0 |
0 |
| T15 |
5207 |
66 |
0 |
0 |
| T16 |
2780 |
225 |
0 |
0 |
| T17 |
0 |
908 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
| T80 |
0 |
360 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T2 T3
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T2 T3
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T3
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
32080489 |
0 |
0 |
| T1 |
2239 |
174 |
0 |
0 |
| T2 |
8037 |
198 |
0 |
0 |
| T3 |
3074 |
391 |
0 |
0 |
| T4 |
47171 |
1477 |
0 |
0 |
| T5 |
0 |
68 |
0 |
0 |
| T12 |
28122 |
1815 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
4760 |
0 |
0 |
| T15 |
5207 |
174 |
0 |
0 |
| T16 |
2780 |
198 |
0 |
0 |
| T17 |
0 |
2101 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
32080489 |
0 |
0 |
| T1 |
2239 |
174 |
0 |
0 |
| T2 |
8037 |
198 |
0 |
0 |
| T3 |
3074 |
391 |
0 |
0 |
| T4 |
47171 |
1477 |
0 |
0 |
| T5 |
0 |
68 |
0 |
0 |
| T12 |
28122 |
1815 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
4760 |
0 |
0 |
| T15 |
5207 |
174 |
0 |
0 |
| T16 |
2780 |
198 |
0 |
0 |
| T17 |
0 |
2101 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T2 T3
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T2 T3
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T3
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Total | Covered | Percent |
|---|
| Conditions | 16 | 10 | 62.50 |
| Logical | 16 | 10 | 62.50 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
16316915 |
0 |
0 |
| T1 |
2239 |
174 |
0 |
0 |
| T2 |
8037 |
198 |
0 |
0 |
| T3 |
3074 |
84 |
0 |
0 |
| T4 |
47171 |
1477 |
0 |
0 |
| T5 |
0 |
68 |
0 |
0 |
| T12 |
28122 |
1815 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
1028 |
0 |
0 |
| T15 |
5207 |
174 |
0 |
0 |
| T16 |
2780 |
198 |
0 |
0 |
| T17 |
0 |
2101 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
16316915 |
0 |
0 |
| T1 |
2239 |
174 |
0 |
0 |
| T2 |
8037 |
198 |
0 |
0 |
| T3 |
3074 |
84 |
0 |
0 |
| T4 |
47171 |
1477 |
0 |
0 |
| T5 |
0 |
68 |
0 |
0 |
| T12 |
28122 |
1815 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
1028 |
0 |
0 |
| T15 |
5207 |
174 |
0 |
0 |
| T16 |
2780 |
198 |
0 |
0 |
| T17 |
0 |
2101 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T2 T3
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T2 T3
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Total | Covered | Percent |
|---|
| Conditions | 24 | 18 | 75.00 |
| Logical | 24 | 18 | 75.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T14,T82 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T14,T82 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
32063331 |
0 |
0 |
| T1 |
2239 |
174 |
0 |
0 |
| T2 |
8037 |
198 |
0 |
0 |
| T3 |
3074 |
391 |
0 |
0 |
| T4 |
47171 |
1477 |
0 |
0 |
| T5 |
0 |
68 |
0 |
0 |
| T12 |
28122 |
1815 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
4760 |
0 |
0 |
| T15 |
5207 |
174 |
0 |
0 |
| T16 |
2780 |
198 |
0 |
0 |
| T17 |
0 |
2101 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
553971663 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
554110382 |
32063331 |
0 |
0 |
| T1 |
2239 |
174 |
0 |
0 |
| T2 |
8037 |
198 |
0 |
0 |
| T3 |
3074 |
391 |
0 |
0 |
| T4 |
47171 |
1477 |
0 |
0 |
| T5 |
0 |
68 |
0 |
0 |
| T12 |
28122 |
1815 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
4760 |
0 |
0 |
| T15 |
5207 |
174 |
0 |
0 |
| T16 |
2780 |
198 |
0 |
0 |
| T17 |
0 |
2101 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
104180957 |
0 |
0 |
| T1 |
2239 |
648 |
0 |
0 |
| T2 |
8037 |
982 |
0 |
0 |
| T3 |
3074 |
186 |
0 |
0 |
| T4 |
47171 |
2996 |
0 |
0 |
| T12 |
28122 |
3500 |
0 |
0 |
| T13 |
49071 |
383 |
0 |
0 |
| T14 |
22376 |
1990 |
0 |
0 |
| T15 |
5207 |
593 |
0 |
0 |
| T16 |
2780 |
882 |
0 |
0 |
| T19 |
1517 |
11 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881 |
881 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
169392386 |
0 |
0 |
| T1 |
2239 |
648 |
0 |
0 |
| T2 |
8037 |
982 |
0 |
0 |
| T3 |
3074 |
836 |
0 |
0 |
| T4 |
47171 |
2858 |
0 |
0 |
| T12 |
28122 |
3490 |
0 |
0 |
| T13 |
49071 |
383 |
0 |
0 |
| T14 |
22376 |
8896 |
0 |
0 |
| T15 |
5207 |
593 |
0 |
0 |
| T16 |
2780 |
882 |
0 |
0 |
| T19 |
1517 |
11 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881 |
881 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
16367779 |
0 |
0 |
| T1 |
2239 |
174 |
0 |
0 |
| T2 |
8037 |
198 |
0 |
0 |
| T3 |
3074 |
84 |
0 |
0 |
| T4 |
47171 |
1477 |
0 |
0 |
| T5 |
0 |
68 |
0 |
0 |
| T12 |
28122 |
1815 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
1028 |
0 |
0 |
| T15 |
5207 |
174 |
0 |
0 |
| T16 |
2780 |
198 |
0 |
0 |
| T17 |
0 |
2101 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881 |
881 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
32099207 |
0 |
0 |
| T1 |
2239 |
174 |
0 |
0 |
| T2 |
8037 |
198 |
0 |
0 |
| T3 |
3074 |
391 |
0 |
0 |
| T4 |
47171 |
1477 |
0 |
0 |
| T5 |
0 |
68 |
0 |
0 |
| T12 |
28122 |
1815 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
4760 |
0 |
0 |
| T15 |
5207 |
174 |
0 |
0 |
| T16 |
2780 |
198 |
0 |
0 |
| T17 |
0 |
2101 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881 |
881 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
27519964 |
0 |
0 |
| T1 |
2239 |
71 |
0 |
0 |
| T2 |
8037 |
148 |
0 |
0 |
| T3 |
3074 |
3 |
0 |
0 |
| T4 |
47171 |
241 |
0 |
0 |
| T5 |
0 |
21 |
0 |
0 |
| T12 |
28122 |
113 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
54 |
0 |
0 |
| T15 |
5207 |
57 |
0 |
0 |
| T16 |
2780 |
123 |
0 |
0 |
| T17 |
0 |
995 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881 |
881 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
46125859 |
0 |
0 |
| T1 |
2239 |
71 |
0 |
0 |
| T2 |
8037 |
148 |
0 |
0 |
| T3 |
3074 |
9 |
0 |
0 |
| T4 |
47171 |
241 |
0 |
0 |
| T5 |
0 |
19 |
0 |
0 |
| T12 |
28122 |
113 |
0 |
0 |
| T13 |
49071 |
0 |
0 |
0 |
| T14 |
22376 |
252 |
0 |
0 |
| T15 |
5207 |
57 |
0 |
0 |
| T16 |
2780 |
123 |
0 |
0 |
| T17 |
0 |
995 |
0 |
0 |
| T19 |
1517 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
555584426 |
555393045 |
0 |
0 |
| T1 |
2239 |
2159 |
0 |
0 |
| T2 |
8037 |
7938 |
0 |
0 |
| T3 |
3074 |
2941 |
0 |
0 |
| T4 |
47171 |
47117 |
0 |
0 |
| T12 |
28122 |
28042 |
0 |
0 |
| T13 |
49071 |
49015 |
0 |
0 |
| T14 |
22376 |
22286 |
0 |
0 |
| T15 |
5207 |
5127 |
0 |
0 |
| T16 |
2780 |
2697 |
0 |
0 |
| T19 |
1517 |
1451 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881 |
881 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |