Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	555584426	10407	0	0
entropy_period_rd_A	555584426	2166	0	0
intr_enable_rd_A	555584426	2940	0	0
prefix_0_rd_A	555584426	2097	0	0
prefix_10_rd_A	555584426	2249	0	0
prefix_1_rd_A	555584426	2132	0	0
prefix_2_rd_A	555584426	2058	0	0
prefix_3_rd_A	555584426	2062	0	0
prefix_4_rd_A	555584426	2101	0	0
prefix_5_rd_A	555584426	2166	0	0
prefix_6_rd_A	555584426	2162	0	0
prefix_7_rd_A	555584426	2120	0	0
prefix_8_rd_A	555584426	2152	0	0
prefix_9_rd_A	555584426	2222	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	10407	0	0
T20	45054	0	0	0
T32	136218	2136	0	0
T33	197356	0	0	0
T57	0	5485	0	0
T64	862	0	0	0
T65	0	174	0	0
T86	167601	0	0	0
T87	178084	0	0	0
T102	176625	0	0	0
T103	80530	0	0	0
T107	56751	0	0	0
T124	0	1	0	0
T125	0	3	0	0
T126	0	1	0	0
T128	0	266	0	0
T131	0	4	0	0
T135	0	97	0	0
T138	0	4	0	0
T140	10092	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2166	0	0
T111	3853	13	0	0
T112	5858	14	0	0
T114	15960	92	0	0
T150	2965	10	0	0
T151	48849	432	0	0
T152	3276	11	0	0
T153	26585	211	0	0
T154	5981	57	0	0
T155	7198	21	0	0
T156	1927	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2940	0	0
T111	3853	13	0	0
T112	5858	50	0	0
T114	15960	114	0	0
T130	1419	10	0	0
T150	2965	9	0	0
T151	48849	422	0	0
T152	3276	5	0	0
T153	26585	191	0	0
T154	5981	12	0	0
T157	3651	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2097	0	0
T111	3853	15	0	0
T112	5858	20	0	0
T114	15960	47	0	0
T150	2965	10	0	0
T151	48849	393	0	0
T152	3276	15	0	0
T153	26585	235	0	0
T154	5981	6	0	0
T155	7198	19	0	0
T156	1927	9	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2249	0	0
T111	3853	16	0	0
T112	5858	19	0	0
T114	15960	58	0	0
T132	15963	2	0	0
T150	2965	6	0	0
T151	48849	462	0	0
T152	3276	1	0	0
T153	26585	200	0	0
T154	5981	5	0	0
T157	3651	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2132	0	0
T111	3853	4	0	0
T112	5858	24	0	0
T114	15960	40	0	0
T150	2965	6	0	0
T151	48849	452	0	0
T152	3276	16	0	0
T153	26585	223	0	0
T154	5981	20	0	0
T155	7198	18	0	0
T156	1927	9	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2058	0	0
T111	3853	9	0	0
T112	5858	19	0	0
T114	15960	42	0	0
T150	2965	7	0	0
T151	48849	427	0	0
T152	3276	5	0	0
T153	26585	201	0	0
T154	5981	56	0	0
T155	7198	14	0	0
T158	11319	44	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2062	0	0
T111	3853	4	0	0
T112	5858	30	0	0
T114	15960	34	0	0
T132	15963	4	0	0
T150	2965	2	0	0
T151	48849	369	0	0
T152	3276	3	0	0
T153	26585	236	0	0
T154	5981	46	0	0
T157	3651	2	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2101	0	0
T111	3853	3	0	0
T112	5858	36	0	0
T114	15960	30	0	0
T150	2965	6	0	0
T151	48849	356	0	0
T152	3276	10	0	0
T153	26585	223	0	0
T154	5981	6	0	0
T155	7198	22	0	0
T157	3651	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2166	0	0
T111	3853	10	0	0
T112	5858	33	0	0
T114	15960	36	0	0
T150	2965	2	0	0
T151	48849	426	0	0
T152	3276	7	0	0
T153	26585	238	0	0
T154	5981	50	0	0
T155	7198	8	0	0
T157	3651	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2162	0	0
T112	5858	31	0	0
T114	15960	69	0	0
T151	48849	439	0	0
T152	3276	9	0	0
T153	26585	204	0	0
T154	5981	1	0	0
T155	7198	12	0	0
T156	1927	5	0	0
T158	11319	44	0	0
T159	1498	6	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2120	0	0
T111	3853	2	0	0
T112	5858	16	0	0
T114	15960	55	0	0
T132	15963	4	0	0
T150	2965	13	0	0
T151	48849	442	0	0
T152	3276	11	0	0
T153	26585	194	0	0
T154	5981	8	0	0
T157	3651	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2152	0	0
T111	3853	4	0	0
T112	5858	32	0	0
T114	15960	32	0	0
T150	2965	4	0	0
T151	48849	461	0	0
T152	3276	12	0	0
T153	26585	233	0	0
T154	5981	19	0	0
T155	7198	10	0	0
T157	3651	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555584426	2222	0	0
T111	3853	7	0	0
T112	5858	32	0	0
T114	15960	48	0	0
T150	2965	7	0	0
T151	48849	403	0	0
T152	3276	4	0	0
T153	26585	193	0	0
T154	5981	15	0	0
T155	7198	15	0	0
T157	3651	9	0	0