Unified Coverage Report :: Module :: prim_subreg_ext

Module : prim_subreg_ext

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_test_kmac_done	100.00	100.00
tb.dut.u_reg.u_intr_test_fifo_empty	100.00	100.00
tb.dut.u_reg.u_intr_test_kmac_err	100.00	100.00
tb.dut.u_reg.u_alert_test_recov_operation_err	100.00	100.00
tb.dut.u_reg.u_alert_test_fatal_fault_err	100.00	100.00
tb.dut.u_reg.u_cfg_regwen	100.00	100.00
tb.dut.u_reg.u_cmd_cmd	100.00	100.00
tb.dut.u_reg.u_cmd_entropy_req	100.00	100.00
tb.dut.u_reg.u_cmd_hash_cnt_clr	100.00	100.00
tb.dut.u_reg.u_cmd_err_processed	100.00	100.00
tb.dut.u_reg.u_status_sha3_idle	100.00	100.00
tb.dut.u_reg.u_status_sha3_absorb	100.00	100.00
tb.dut.u_reg.u_status_sha3_squeeze	100.00	100.00
tb.dut.u_reg.u_status_fifo_depth	100.00	100.00
tb.dut.u_reg.u_status_fifo_empty	100.00	100.00
tb.dut.u_reg.u_status_fifo_full	100.00	100.00
tb.dut.u_reg.u_status_alert_fatal_fault	100.00	100.00
tb.dut.u_reg.u_status_alert_recov_ctrl_update_err	100.00	100.00
tb.dut.u_reg.u_entropy_seed	100.00	100.00
tb.dut.u_reg.u_key_share0_0	100.00	100.00
tb.dut.u_reg.u_key_share0_1	100.00	100.00
tb.dut.u_reg.u_key_share0_2	100.00	100.00
tb.dut.u_reg.u_key_share0_3	100.00	100.00
tb.dut.u_reg.u_key_share0_4	100.00	100.00
tb.dut.u_reg.u_key_share0_5	100.00	100.00
tb.dut.u_reg.u_key_share0_6	100.00	100.00
tb.dut.u_reg.u_key_share0_7	100.00	100.00
tb.dut.u_reg.u_key_share0_8	100.00	100.00
tb.dut.u_reg.u_key_share0_9	100.00	100.00
tb.dut.u_reg.u_key_share0_10	100.00	100.00
tb.dut.u_reg.u_key_share0_11	100.00	100.00
tb.dut.u_reg.u_key_share0_12	100.00	100.00
tb.dut.u_reg.u_key_share0_13	100.00	100.00
tb.dut.u_reg.u_key_share0_14	100.00	100.00
tb.dut.u_reg.u_key_share0_15	100.00	100.00
tb.dut.u_reg.u_key_share1_0	100.00	100.00
tb.dut.u_reg.u_key_share1_1	100.00	100.00
tb.dut.u_reg.u_key_share1_2	100.00	100.00
tb.dut.u_reg.u_key_share1_3	100.00	100.00
tb.dut.u_reg.u_key_share1_4	100.00	100.00
tb.dut.u_reg.u_key_share1_5	100.00	100.00
tb.dut.u_reg.u_key_share1_6	100.00	100.00
tb.dut.u_reg.u_key_share1_7	100.00	100.00
tb.dut.u_reg.u_key_share1_8	100.00	100.00
tb.dut.u_reg.u_key_share1_9	100.00	100.00
tb.dut.u_reg.u_key_share1_10	100.00	100.00
tb.dut.u_reg.u_key_share1_11	100.00	100.00
tb.dut.u_reg.u_key_share1_12	100.00	100.00
tb.dut.u_reg.u_key_share1_13	100.00	100.00
tb.dut.u_reg.u_key_share1_14	100.00	100.00
tb.dut.u_reg.u_key_share1_15	100.00	100.00

---

Module Instance : tb.dut.u_reg.u_intr_test_kmac_done

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_intr_test_fifo_empty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_intr_test_kmac_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_alert_test_recov_operation_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_alert_test_fatal_fault_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_cfg_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_cmd_cmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_cmd_entropy_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_cmd_hash_cnt_clr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_cmd_err_processed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_sha3_idle

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_sha3_absorb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_sha3_squeeze

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_fifo_depth

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_fifo_empty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_fifo_full

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_alert_fatal_fault

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_alert_recov_ctrl_update_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_entropy_seed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share0_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_key_share1_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.87	100.00	99.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_subreg_ext

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T19 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_kmac_done

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T32 T57 T127 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_fifo_empty

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T32 T57 T127 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_intr_test_kmac_err

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T32 T57 T127 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_alert_test_recov_operation_err

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T19 T51 T32 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_alert_test_fatal_fault_err

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T19 T51 T32 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_cfg_regwen

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T12 

Line Coverage for Instance : tb.dut.u_reg.u_cmd_cmd

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_cmd_entropy_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_cmd_hash_cnt_clr

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_cmd_err_processed

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_status_sha3_idle

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_sha3_absorb

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_sha3_squeeze

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T4 
27         1/1            assign qs = d;
           Tests:       T1 T2 T4 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_fifo_depth

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_fifo_empty

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_fifo_full

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_alert_fatal_fault

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_alert_recov_ctrl_update_err

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_entropy_seed

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T3 T5 T6 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_0

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_1

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_2

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_3

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_4

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_5

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_6

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_7

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_8

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_9

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_10

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_11

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_12

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_13

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_14

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share0_15

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_0

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_1

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_2

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_3

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_4

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_5

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_6

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_7

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_8

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_9

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_10

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_11

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_12

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_13

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_14

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_key_share1_15

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T4 
30         unreachable    assign qre = re;