Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44136707	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

53494603

1

T1

306

T2

543

T3

426

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52076328	1			T1	223		T2	495		T3	349
values[0x0]	22074006	1			T1	71		T2	223		T3	152
values[0x1]	23480976	1			T1	71		T2	226		T3	176

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34258328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63372982

1

T1

324

T2

637

T3

486

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	309495	1			T1	6		T3	1		T12	1
valid_sources[0x01]	306881	1			T2	15		T3	1		T12	2
valid_sources[0x02]	993964	1			T1	1		T2	6		T12	1
valid_sources[0x03]	310296	1			T2	4		T3	2		T12	2
valid_sources[0x04]	386907	1			T3	3		T12	1		T13	79
valid_sources[0x05]	440847	1			T1	1		T2	6		T12	1
valid_sources[0x06]	315090	1			T1	1		T2	1		T3	4
valid_sources[0x07]	305786	1			T3	4		T13	51		T14	2
valid_sources[0x08]	306539	1			T2	6		T3	4		T12	2
valid_sources[0x09]	402263	1			T2	12		T3	7		T12	1
valid_sources[0x0a]	317690	1			T1	1		T2	8		T12	1
valid_sources[0x0b]	310022	1			T1	1		T2	8		T3	2
valid_sources[0x0c]	309683	1			T12	6		T13	109		T4	38
valid_sources[0x0d]	310819	1			T2	3		T3	2		T12	1
valid_sources[0x0e]	307380	1			T1	6		T2	3		T3	1
valid_sources[0x0f]	308661	1			T1	4		T2	6		T12	2
valid_sources[0x10]	501678	1			T12	3		T13	33		T14	1
valid_sources[0x11]	307459	1			T12	3		T13	91		T4	3
valid_sources[0x12]	318542	1			T2	10		T3	4		T12	2
valid_sources[0x13]	375193	1			T3	3		T12	1		T13	69
valid_sources[0x14]	511910	1			T2	3		T3	2		T12	2
valid_sources[0x15]	551277	1			T1	1		T2	4		T3	1
valid_sources[0x16]	304380	1			T2	4		T3	6		T12	4
valid_sources[0x17]	809884	1			T1	1		T2	4		T3	3
valid_sources[0x18]	309750	1			T1	1		T2	6		T12	3
valid_sources[0x19]	312591	1			T2	4		T3	3		T13	34
valid_sources[0x1a]	370235	1			T1	1		T2	2		T3	2
valid_sources[0x1b]	402288	1			T1	2		T2	9		T12	1
valid_sources[0x1c]	440650	1			T2	3		T3	2		T12	1
valid_sources[0x1d]	337468	1			T2	1		T3	4		T12	2
valid_sources[0x1e]	308872	1			T2	2		T3	4		T12	2
valid_sources[0x1f]	305475	1			T1	6		T3	1		T12	1
valid_sources[0x20]	308507	1			T1	2		T2	26		T12	4
valid_sources[0x21]	311587	1			T2	7		T3	4		T12	3
valid_sources[0x22]	945362	1			T1	1		T2	2		T3	1
valid_sources[0x23]	310167	1			T1	5		T2	6		T3	2
valid_sources[0x24]	314212	1			T1	4		T12	4		T13	47
valid_sources[0x25]	480315	1			T1	4		T2	5		T3	2
valid_sources[0x26]	308267	1			T1	1		T2	8		T3	13
valid_sources[0x27]	309802	1			T2	1		T3	6		T13	27
valid_sources[0x28]	309886	1			T1	2		T3	1		T12	2
valid_sources[0x29]	307323	1			T3	1		T13	26		T14	2
valid_sources[0x2a]	421845	1			T13	71		T14	2		T4	3
valid_sources[0x2b]	445976	1			T1	2		T12	2		T13	33
valid_sources[0x2c]	306668	1			T1	3		T2	3		T3	5
valid_sources[0x2d]	311300	1			T3	8		T13	65		T4	6
valid_sources[0x2e]	306077	1			T1	3		T2	7		T3	3
valid_sources[0x2f]	760886	1			T1	3		T2	4		T12	1
valid_sources[0x30]	320959	1			T1	3		T12	1		T13	79
valid_sources[0x31]	937546	1			T2	15		T3	2		T12	1
valid_sources[0x32]	308523	1			T1	1		T2	1		T3	6
valid_sources[0x33]	307200	1			T1	3		T2	2		T3	2
valid_sources[0x34]	311621	1			T3	4		T12	2		T13	123
valid_sources[0x35]	348412	1			T2	6		T3	4		T12	1
valid_sources[0x36]	307165	1			T3	11		T13	28		T14	1
valid_sources[0x37]	310037	1			T1	3		T3	1		T12	2
valid_sources[0x38]	307678	1			T1	1		T2	1		T3	8
valid_sources[0x39]	404271	1			T1	1		T3	1		T12	1
valid_sources[0x3a]	366229	1			T2	1		T3	2		T12	2
valid_sources[0x3b]	834978	1			T1	6		T2	4		T13	30
valid_sources[0x3c]	845326	1			T1	4		T12	3		T13	66
valid_sources[0x3d]	309689	1			T1	2		T2	5		T12	1
valid_sources[0x3e]	309980	1			T1	4		T2	4		T3	2
valid_sources[0x3f]	551346	1			T3	2		T12	3		T13	109
valid_sources[0x40]	306427	1			T1	3		T12	1		T13	19
valid_sources[0x41]	312354	1			T1	2		T2	2		T3	3
valid_sources[0x42]	306149	1			T1	2		T2	6		T3	5
valid_sources[0x43]	306821	1			T1	1		T3	11		T12	4
valid_sources[0x44]	304703	1			T2	1		T3	17		T12	1
valid_sources[0x45]	311748	1			T1	6		T2	17		T3	8
valid_sources[0x46]	313332	1			T3	3		T12	4		T13	66
valid_sources[0x47]	307149	1			T1	2		T2	7		T3	1
valid_sources[0x48]	323855	1			T1	1		T12	2		T13	222
valid_sources[0x49]	312525	1			T2	1		T3	7		T13	5
valid_sources[0x4a]	308117	1			T1	2		T2	10		T13	42
valid_sources[0x4b]	311208	1			T1	1		T2	18		T3	1
valid_sources[0x4c]	314864	1			T1	2		T3	7		T12	7
valid_sources[0x4d]	308182	1			T3	2		T12	4		T13	20
valid_sources[0x4e]	313279	1			T1	1		T2	6		T3	1
valid_sources[0x4f]	532092	1			T2	4		T3	1		T12	3
valid_sources[0x50]	439661	1			T1	1		T2	4		T3	3
valid_sources[0x51]	313299	1			T2	5		T3	2		T12	1
valid_sources[0x52]	432082	1			T1	1		T3	5		T12	3
valid_sources[0x53]	308756	1			T2	6		T3	3		T12	1
valid_sources[0x54]	307781	1			T1	1		T2	1		T3	1
valid_sources[0x55]	343186	1			T12	2		T13	124		T4	13
valid_sources[0x56]	347986	1			T2	3		T3	2		T13	79
valid_sources[0x57]	305178	1			T2	9		T3	1		T13	64
valid_sources[0x58]	308201	1			T1	1		T3	7		T12	2
valid_sources[0x59]	306088	1			T1	1		T2	5		T3	5
valid_sources[0x5a]	308059	1			T2	7		T3	2		T12	1
valid_sources[0x5b]	306858	1			T1	3		T2	1		T12	1
valid_sources[0x5c]	566367	1			T3	2		T13	41		T4	9
valid_sources[0x5d]	345684	1			T3	1		T13	45		T14	1
valid_sources[0x5e]	309007	1			T1	1		T2	3		T12	1
valid_sources[0x5f]	308546	1			T1	4		T2	3		T3	7
valid_sources[0x60]	311531	1			T1	5		T2	12		T3	4
valid_sources[0x61]	308338	1			T3	4		T12	1		T13	99
valid_sources[0x62]	367488	1			T1	7		T2	13		T12	2
valid_sources[0x63]	311735	1			T2	8		T3	1		T13	58
valid_sources[0x64]	306750	1			T2	2		T3	2		T13	79
valid_sources[0x65]	307693	1			T1	1		T3	3		T12	1
valid_sources[0x66]	309417	1			T1	1		T2	11		T3	8
valid_sources[0x67]	315829	1			T1	3		T2	3		T3	2
valid_sources[0x68]	304810	1			T2	11		T12	1		T13	55
valid_sources[0x69]	311701	1			T1	2		T3	4		T12	1
valid_sources[0x6a]	418782	1			T1	2		T2	2		T13	67
valid_sources[0x6b]	478953	1			T1	2		T12	3		T13	58
valid_sources[0x6c]	307666	1			T1	3		T2	2		T12	2
valid_sources[0x6d]	308622	1			T2	9		T3	3		T12	1
valid_sources[0x6e]	311242	1			T1	2		T12	1		T13	82
valid_sources[0x6f]	435762	1			T1	1		T2	6		T12	1
valid_sources[0x70]	403795	1			T3	5		T12	1		T13	23
valid_sources[0x71]	308607	1			T3	10		T12	1		T13	44
valid_sources[0x72]	582218	1			T3	6		T13	17		T14	1
valid_sources[0x73]	322613	1			T2	1		T3	1		T12	1
valid_sources[0x74]	408724	1			T1	4		T3	2		T12	1
valid_sources[0x75]	311410	1			T1	3		T2	4		T12	1
valid_sources[0x76]	593174	1			T1	2		T2	6		T3	1
valid_sources[0x77]	309188	1			T2	5		T3	1		T12	1
valid_sources[0x78]	306030	1			T3	4		T12	1		T13	64
valid_sources[0x79]	307725	1			T1	2		T2	2		T3	3
valid_sources[0x7a]	304235	1			T1	1		T2	1		T3	2
valid_sources[0x7b]	822036	1			T1	6		T13	30		T4	2
valid_sources[0x7c]	427816	1			T2	2		T12	1		T13	53
valid_sources[0x7d]	314172	1			T2	3		T12	2		T13	20
valid_sources[0x7e]	313406	1			T1	4		T12	2		T13	81
valid_sources[0x7f]	312257	1			T2	5		T3	4		T12	3
valid_sources[0x80]	307833	1			T1	1		T2	1		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24956439

1

T1

188

T2

282

T3

221

values[0x0]

all_enables

biggest_size

14982233

1

T1

61

T2

141

T3

104

values[0x1]

all_enables

biggest_size

13555931

1

T1

57

T2

120

T3

101