Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44242913

1

T1

59

T2

401

T3

251

full_word

53501241

1

T1

306

T2

543

T3

426

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	97743894	1			T1	365		T2	944		T3	677
auto[TlIntgErrCmd]	83	1			T108	6		T109	2		T110	7
auto[TlIntgErrData]	85	1			T108	9		T109	2		T110	6
auto[TlIntgErrBoth]	92	1			T108	5		T109	6		T110	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52102754

1

T1

223

T2

495

T3

349

auto[1]

45641400

1

T1

142

T2

449

T3

328

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	27144175	1			T1	35		T2	213		T3	128
auto[TlIntgErrNone]	partial	auto[1]	17098496	1			T1	24		T2	188		T3	123
auto[TlIntgErrNone]	full_word	auto[0]	24958471	1			T1	188		T2	282		T3	221
auto[TlIntgErrNone]	full_word	auto[1]	28542752	1			T1	118		T2	261		T3	205
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T108	2		T109	1		T110	4
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T108	3		T110	3		T155	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T109	1		T160	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T108	1		T158	1		T161	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T108	5		T109	2		T110	3
auto[TlIntgErrData]	partial	auto[1]	36	1			T108	3		T110	3		T155	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T108	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T160	2		T162	1		T161	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T108	2		T109	2		T110	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T108	3		T109	4		T110	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T163	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T110	1		T158	1		T164	1