Module Definition
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Module : sha3pad_assert_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sha3pad_assert_cov_if 100.00 100.00



Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sha3pad_assert_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ProcessToRun_A 589893837 56261 0 0
RunThenComplete_M 589893837 790229 0 0


ProcessToRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 589893837 56261 0 0
T1 1973 2 0 0
T2 11133 3 0 0
T3 5966 3 0 0
T4 40188 6 0 0
T12 44605 6 0 0
T13 53834 21 0 0
T14 36189 16 0 0
T15 130636 40 0 0
T16 124586 16 0 0
T17 0 50 0 0
T18 2465 0 0 0

RunThenComplete_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 589893837 790229 0 0
T1 1973 6 0 0
T2 11133 11 0 0
T3 5966 10 0 0
T4 40188 30 0 0
T12 44605 18 0 0
T13 53834 106 0 0
T14 36189 63 0 0
T15 130636 201 0 0
T16 124586 86 0 0
T17 0 247 0 0
T18 2465 0 0 0