Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	591336541	18570	0	0
entropy_period_rd_A	591336541	1944	0	0
intr_enable_rd_A	591336541	2783	0	0
prefix_0_rd_A	591336541	2153	0	0
prefix_10_rd_A	591336541	2171	0	0
prefix_1_rd_A	591336541	2102	0	0
prefix_2_rd_A	591336541	2380	0	0
prefix_3_rd_A	591336541	2250	0	0
prefix_4_rd_A	591336541	2181	0	0
prefix_5_rd_A	591336541	2178	0	0
prefix_6_rd_A	591336541	2270	0	0
prefix_7_rd_A	591336541	2364	0	0
prefix_8_rd_A	591336541	2189	0	0
prefix_9_rd_A	591336541	2294	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	18570	0	0
T11	268515	0	0	0
T26	239164	0	0	0
T27	296555	3733	0	0
T29	162875	0	0	0
T43	0	5229	0	0
T46	0	2585	0	0
T52	0	697	0	0
T76	393310	0	0	0
T80	0	1426	0	0
T114	0	1941	0	0
T115	0	124	0	0
T116	0	3	0	0
T117	0	222	0	0
T118	0	7	0	0
T119	137298	0	0	0
T120	2922	0	0	0
T121	2782	0	0	0
T122	40748	0	0	0
T123	100992	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	1944	0	0
T7	50918	0	0	0
T52	306754	16	0	0
T92	0	11	0	0
T94	0	29	0	0
T95	0	2	0	0
T109	0	46	0	0
T112	0	1	0	0
T116	0	2	0	0
T118	0	24	0	0
T133	0	13	0	0
T134	0	8	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2783	0	0
T7	50918	0	0	0
T52	306754	17	0	0
T92	0	9	0	0
T94	0	11	0	0
T95	0	14	0	0
T109	0	97	0	0
T112	0	9	0	0
T116	0	9	0	0
T118	0	29	0	0
T133	0	15	0	0
T134	0	14	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2153	0	0
T7	50918	0	0	0
T52	306754	4	0	0
T92	0	7	0	0
T94	0	10	0	0
T95	0	5	0	0
T109	0	49	0	0
T112	0	4	0	0
T116	0	11	0	0
T118	0	23	0	0
T134	0	6	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0
T143	0	141	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2171	0	0
T7	50918	0	0	0
T52	306754	21	0	0
T92	0	5	0	0
T94	0	18	0	0
T95	0	8	0	0
T109	0	31	0	0
T112	0	2	0	0
T116	0	9	0	0
T118	0	23	0	0
T133	0	9	0	0
T134	0	7	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2102	0	0
T7	50918	0	0	0
T52	306754	18	0	0
T92	0	9	0	0
T94	0	5	0	0
T95	0	9	0	0
T109	0	23	0	0
T112	0	3	0	0
T116	0	2	0	0
T118	0	17	0	0
T133	0	5	0	0
T134	0	10	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2380	0	0
T7	50918	0	0	0
T52	306754	18	0	0
T92	0	4	0	0
T94	0	6	0	0
T95	0	8	0	0
T109	0	42	0	0
T112	0	4	0	0
T116	0	10	0	0
T118	0	11	0	0
T133	0	1	0	0
T134	0	8	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2250	0	0
T7	50918	0	0	0
T52	306754	30	0	0
T92	0	17	0	0
T94	0	2	0	0
T95	0	12	0	0
T109	0	43	0	0
T112	0	6	0	0
T116	0	7	0	0
T118	0	9	0	0
T133	0	9	0	0
T134	0	8	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2181	0	0
T7	50918	0	0	0
T52	306754	24	0	0
T92	0	5	0	0
T94	0	20	0	0
T95	0	10	0	0
T109	0	44	0	0
T112	0	7	0	0
T116	0	5	0	0
T118	0	22	0	0
T133	0	10	0	0
T134	0	15	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2178	0	0
T7	50918	0	0	0
T52	306754	22	0	0
T92	0	9	0	0
T94	0	9	0	0
T95	0	13	0	0
T109	0	53	0	0
T112	0	1	0	0
T116	0	7	0	0
T118	0	14	0	0
T133	0	1	0	0
T134	0	8	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2270	0	0
T7	50918	0	0	0
T52	306754	25	0	0
T92	0	15	0	0
T94	0	19	0	0
T95	0	12	0	0
T109	0	41	0	0
T112	0	7	0	0
T116	0	15	0	0
T118	0	17	0	0
T133	0	8	0	0
T134	0	4	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2364	0	0
T7	50918	0	0	0
T52	306754	18	0	0
T92	0	10	0	0
T94	0	14	0	0
T109	0	36	0	0
T112	0	7	0	0
T116	0	8	0	0
T118	0	16	0	0
T133	0	10	0	0
T134	0	5	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0
T143	0	108	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2189	0	0
T7	50918	0	0	0
T52	306754	36	0	0
T92	0	3	0	0
T94	0	23	0	0
T95	0	14	0	0
T109	0	57	0	0
T112	0	3	0	0
T116	0	7	0	0
T118	0	13	0	0
T133	0	6	0	0
T134	0	9	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591336541	2294	0	0
T7	50918	0	0	0
T52	306754	21	0	0
T92	0	12	0	0
T94	0	35	0	0
T95	0	12	0	0
T109	0	32	0	0
T112	0	8	0	0
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T118	0	25	0	0
T133	0	11	0	0
T134	0	7	0	0
T135	167492	0	0	0
T136	1128	0	0	0
T137	17940	0	0	0
T138	81139	0	0	0
T139	47351	0	0	0
T140	54008	0	0	0
T141	200607	0	0	0
T142	269175	0	0	0