Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46276480	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

55213400

1

T1

4158

T2

533

T3

551

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54625587	1			T1	3350		T2	489		T3	427
values[0x0]	22697953	1			T1	783		T2	211		T3	188
values[0x1]	24166340	1			T1	779		T2	235		T3	194

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35933504	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65556376

1

T1

4337

T2

617

T3

611

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	318383	1			T1	23		T2	5		T3	2
valid_sources[0x01]	357239	1			T1	25		T2	2		T3	3
valid_sources[0x02]	317760	1			T1	18		T3	6		T12	33
valid_sources[0x03]	421245	1			T1	11		T3	3		T12	60
valid_sources[0x04]	321184	1			T1	19		T3	1		T12	53
valid_sources[0x05]	334219	1			T1	12		T3	5		T12	99
valid_sources[0x06]	432012	1			T1	19		T12	31		T13	67
valid_sources[0x07]	352198	1			T1	13		T3	3		T12	6
valid_sources[0x08]	320560	1			T1	14		T12	48		T13	161
valid_sources[0x09]	451301	1			T1	21		T3	2		T12	110
valid_sources[0x0a]	349712	1			T1	32		T3	2		T12	111
valid_sources[0x0b]	1155414	1			T1	12		T3	7		T12	67
valid_sources[0x0c]	322250	1			T1	14		T2	4		T3	2
valid_sources[0x0d]	322466	1			T1	26		T3	2		T12	77
valid_sources[0x0e]	319836	1			T1	39		T3	1		T12	59
valid_sources[0x0f]	314676	1			T1	19		T12	77		T13	135
valid_sources[0x10]	318194	1			T1	17		T2	6		T3	5
valid_sources[0x11]	321532	1			T1	14		T3	1		T12	45
valid_sources[0x12]	564856	1			T1	22		T3	2		T12	11
valid_sources[0x13]	324604	1			T1	26		T2	14		T12	35
valid_sources[0x14]	315072	1			T1	19		T3	6		T12	13
valid_sources[0x15]	384269	1			T1	17		T2	1		T3	2
valid_sources[0x16]	323956	1			T1	16		T3	6		T12	49
valid_sources[0x17]	319844	1			T1	31		T12	75		T13	93
valid_sources[0x18]	317925	1			T1	11		T3	2		T12	195
valid_sources[0x19]	318246	1			T1	15		T3	3		T12	57
valid_sources[0x1a]	314897	1			T1	15		T3	2		T12	31
valid_sources[0x1b]	318676	1			T1	23		T2	12		T3	3
valid_sources[0x1c]	320551	1			T1	21		T2	26		T3	1
valid_sources[0x1d]	320183	1			T1	10		T3	2		T12	42
valid_sources[0x1e]	321018	1			T1	20		T2	8		T3	6
valid_sources[0x1f]	326985	1			T1	28		T3	2		T12	119
valid_sources[0x20]	317096	1			T1	15		T3	2		T12	49
valid_sources[0x21]	420479	1			T1	21		T3	12		T12	42
valid_sources[0x22]	348593	1			T1	13		T3	2		T12	22
valid_sources[0x23]	320388	1			T1	9		T2	11		T3	9
valid_sources[0x24]	427280	1			T1	8		T2	4		T3	7
valid_sources[0x25]	319648	1			T1	22		T12	21		T13	76
valid_sources[0x26]	318515	1			T1	14		T2	17		T3	2
valid_sources[0x27]	315120	1			T1	21		T3	4		T12	36
valid_sources[0x28]	316901	1			T1	19		T12	87		T13	55
valid_sources[0x29]	319095	1			T1	20		T2	11		T3	2
valid_sources[0x2a]	314971	1			T1	20		T2	3		T3	4
valid_sources[0x2b]	473947	1			T1	13		T2	4		T3	1
valid_sources[0x2c]	320108	1			T1	10		T3	3		T12	46
valid_sources[0x2d]	316101	1			T1	35		T3	4		T12	43
valid_sources[0x2e]	317548	1			T1	6		T3	2		T12	56
valid_sources[0x2f]	321124	1			T1	19		T12	35		T13	64
valid_sources[0x30]	385551	1			T1	15		T3	8		T12	34
valid_sources[0x31]	320292	1			T1	20		T3	1		T12	60
valid_sources[0x32]	323719	1			T1	26		T3	4		T12	32
valid_sources[0x33]	319093	1			T1	17		T3	2		T12	32
valid_sources[0x34]	322125	1			T1	16		T3	2		T12	35
valid_sources[0x35]	333128	1			T1	25		T2	2		T3	5
valid_sources[0x36]	414595	1			T1	4		T3	6		T12	45
valid_sources[0x37]	321741	1			T1	27		T3	1		T12	19
valid_sources[0x38]	1156362	1			T1	9		T2	1		T3	2
valid_sources[0x39]	336010	1			T1	21		T3	1		T12	47
valid_sources[0x3a]	352661	1			T1	20		T2	12		T3	2
valid_sources[0x3b]	316777	1			T1	24		T3	4		T12	24
valid_sources[0x3c]	340913	1			T1	26		T12	56		T13	153
valid_sources[0x3d]	319302	1			T1	39		T2	23		T12	73
valid_sources[0x3e]	354453	1			T1	16		T3	1		T12	27
valid_sources[0x3f]	326071	1			T1	22		T3	1		T12	164
valid_sources[0x40]	1183408	1			T1	18		T3	4		T12	78
valid_sources[0x41]	935866	1			T1	26		T3	1		T12	71
valid_sources[0x42]	498934	1			T1	21		T3	2		T12	42
valid_sources[0x43]	337716	1			T1	20		T3	2		T12	79
valid_sources[0x44]	318534	1			T1	20		T3	3		T12	63
valid_sources[0x45]	319237	1			T1	26		T2	1		T3	3
valid_sources[0x46]	318977	1			T1	12		T3	5		T12	67
valid_sources[0x47]	438669	1			T1	21		T12	43		T13	87
valid_sources[0x48]	1152601	1			T1	22		T3	1		T12	92
valid_sources[0x49]	319256	1			T1	20		T2	14		T12	21
valid_sources[0x4a]	316214	1			T1	18		T3	7		T12	84
valid_sources[0x4b]	319573	1			T1	17		T3	6		T12	43
valid_sources[0x4c]	681758	1			T1	25		T2	6		T3	3
valid_sources[0x4d]	317723	1			T1	13		T3	1		T12	94
valid_sources[0x4e]	435716	1			T1	19		T3	1		T12	144
valid_sources[0x4f]	321936	1			T1	16		T3	3		T12	44
valid_sources[0x50]	319617	1			T1	21		T3	1		T12	38
valid_sources[0x51]	452518	1			T1	20		T2	8		T3	3
valid_sources[0x52]	319332	1			T1	18		T2	16		T3	4
valid_sources[0x53]	314998	1			T1	14		T2	4		T3	3
valid_sources[0x54]	314633	1			T1	18		T3	1		T12	21
valid_sources[0x55]	318709	1			T1	10		T3	4		T12	52
valid_sources[0x56]	328510	1			T1	21		T3	4		T12	122
valid_sources[0x57]	355441	1			T1	11		T3	5		T12	36
valid_sources[0x58]	388118	1			T1	9		T3	3		T12	70
valid_sources[0x59]	318937	1			T1	10		T2	9		T3	1
valid_sources[0x5a]	319993	1			T1	18		T3	3		T12	91
valid_sources[0x5b]	475335	1			T1	20		T3	4		T12	19
valid_sources[0x5c]	320411	1			T1	17		T2	4		T12	120
valid_sources[0x5d]	319879	1			T1	16		T3	4		T12	44
valid_sources[0x5e]	316343	1			T1	21		T3	5		T12	13
valid_sources[0x5f]	316515	1			T1	14		T3	2		T12	25
valid_sources[0x60]	318807	1			T1	27		T3	6		T12	50
valid_sources[0x61]	319381	1			T1	22		T3	6		T12	102
valid_sources[0x62]	317084	1			T1	13		T3	4		T12	68
valid_sources[0x63]	318937	1			T1	18		T3	3		T12	78
valid_sources[0x64]	493128	1			T1	12		T3	4		T12	60
valid_sources[0x65]	1266778	1			T1	19		T3	1		T12	21
valid_sources[0x66]	314177	1			T1	14		T3	4		T12	31
valid_sources[0x67]	337947	1			T1	18		T3	3		T12	33
valid_sources[0x68]	321017	1			T1	20		T2	4		T3	3
valid_sources[0x69]	852339	1			T1	29		T3	5		T12	113
valid_sources[0x6a]	314408	1			T1	12		T3	2		T12	68
valid_sources[0x6b]	339160	1			T1	19		T2	19		T3	3
valid_sources[0x6c]	449436	1			T1	30		T3	6		T12	48
valid_sources[0x6d]	317673	1			T1	24		T2	3		T3	1
valid_sources[0x6e]	324880	1			T1	18		T2	3		T3	8
valid_sources[0x6f]	317235	1			T1	24		T2	6		T3	5
valid_sources[0x70]	320476	1			T1	21		T2	5		T3	1
valid_sources[0x71]	314894	1			T1	18		T12	80		T13	49
valid_sources[0x72]	319809	1			T1	12		T2	12		T3	4
valid_sources[0x73]	315768	1			T1	10		T2	22		T3	3
valid_sources[0x74]	320998	1			T1	17		T3	3		T12	17
valid_sources[0x75]	317110	1			T1	13		T3	3		T12	54
valid_sources[0x76]	321540	1			T1	39		T2	21		T3	7
valid_sources[0x77]	318950	1			T1	23		T3	3		T12	34
valid_sources[0x78]	320187	1			T1	28		T2	4		T3	4
valid_sources[0x79]	1862225	1			T1	12		T3	2		T12	15
valid_sources[0x7a]	315220	1			T1	12		T3	3		T12	16
valid_sources[0x7b]	316872	1			T1	23		T3	4		T12	85
valid_sources[0x7c]	326279	1			T1	27		T2	10		T3	5
valid_sources[0x7d]	317065	1			T1	22		T2	19		T3	3
valid_sources[0x7e]	318391	1			T1	12		T3	5		T12	62
valid_sources[0x7f]	553845	1			T1	11		T2	17		T3	1
valid_sources[0x80]	317376	1			T1	14		T3	3		T12	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26219992

1

T1

2920

T2

280

T3

267

values[0x0]

all_enables

biggest_size

15242673

1

T1

632

T2

133

T3

146

values[0x1]

all_enables

biggest_size

13750735

1

T1

606

T2

120

T3

138