Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

46357135

1

T1

754

T2

402

T3

258

full_word

55218401

1

T1

4158

T2

533

T3

551

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	101575256	1			T1	4912		T2	935		T3	809
auto[TlIntgErrCmd]	85	1			T119	1		T120	3		T121	2
auto[TlIntgErrData]	96	1			T119	6		T120	2		T121	3
auto[TlIntgErrBoth]	99	1			T119	13		T120	5		T121	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54644029

1

T1

3350

T2

489

T3

427

auto[1]

46931507

1

T1

1562

T2

446

T3

382

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	28422517	1			T1	430		T2	209		T3	160
auto[TlIntgErrNone]	partial	auto[1]	17934362	1			T1	324		T2	193		T3	98
auto[TlIntgErrNone]	full_word	auto[0]	26221383	1			T1	2920		T2	280		T3	267
auto[TlIntgErrNone]	full_word	auto[1]	28996994	1			T1	1238		T2	253		T3	284
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T121	1		T169	2		T167	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T119	1		T120	3		T121	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T174	1		T175	1		T173	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T176	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	46	1			T119	2		T120	1		T121	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T119	3		T121	2		T169	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T119	1		T169	1		T177	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T120	1		T167	1		T177	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T119	6		T120	3		T121	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T119	6		T120	2		T121	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T167	1		T168	1		T177	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T119	1		T178	1		T170	1