Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	646338836	14965	0	0
entropy_period_rd_A	646338836	2025	0	0
intr_enable_rd_A	646338836	2650	0	0
prefix_0_rd_A	646338836	2247	0	0
prefix_10_rd_A	646338836	2183	0	0
prefix_1_rd_A	646338836	2213	0	0
prefix_2_rd_A	646338836	2093	0	0
prefix_3_rd_A	646338836	2229	0	0
prefix_4_rd_A	646338836	2179	0	0
prefix_5_rd_A	646338836	2324	0	0
prefix_6_rd_A	646338836	2089	0	0
prefix_7_rd_A	646338836	2328	0	0
prefix_8_rd_A	646338836	2244	0	0
prefix_9_rd_A	646338836	2339	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	14965	0	0
T27	239145	0	0	0
T30	174879	0	0	0
T31	975467	0	0	0
T51	0	4194	0	0
T52	0	5374	0	0
T59	304893	1153	0	0
T72	22945	0	0	0
T119	0	2	0	0
T120	0	1	0	0
T125	0	132	0	0
T126	0	4	0	0
T127	0	208	0	0
T128	0	2	0	0
T129	0	202	0	0
T132	327754	0	0	0
T133	179073	0	0	0
T134	247895	0	0	0
T135	34886	0	0	0
T136	88106	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2025	0	0
T92	4066	11	0	0
T93	7482	43	0	0
T103	2612	13	0	0
T105	10451	90	0	0
T119	23110	111	0	0
T121	12707	93	0	0
T128	4326	6	0	0
T148	1913	10	0	0
T149	72274	103	0	0
T150	12470	68	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2650	0	0
T92	4066	5	0	0
T93	7482	32	0	0
T103	2612	5	0	0
T105	10451	93	0	0
T119	23110	213	0	0
T121	12707	29	0	0
T128	4326	6	0	0
T148	1913	1	0	0
T149	72274	222	0	0
T150	12470	48	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2247	0	0
T92	4066	17	0	0
T93	7482	30	0	0
T103	2612	10	0	0
T105	10451	54	0	0
T119	23110	99	0	0
T121	12707	45	0	0
T128	4326	5	0	0
T148	1913	9	0	0
T149	72274	225	0	0
T150	12470	48	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2183	0	0
T92	4066	18	0	0
T93	7482	28	0	0
T103	2612	3	0	0
T105	10451	44	0	0
T119	23110	57	0	0
T121	12707	23	0	0
T128	4326	2	0	0
T148	1913	6	0	0
T149	72274	238	0	0
T150	12470	11	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2213	0	0
T92	4066	17	0	0
T93	7482	25	0	0
T103	2612	4	0	0
T105	10451	43	0	0
T119	23110	82	0	0
T121	12707	52	0	0
T128	4326	4	0	0
T148	1913	3	0	0
T149	72274	229	0	0
T150	12470	75	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2093	0	0
T92	4066	11	0	0
T93	7482	23	0	0
T103	2612	4	0	0
T105	10451	37	0	0
T119	23110	77	0	0
T121	12707	32	0	0
T128	4326	2	0	0
T148	1913	5	0	0
T149	72274	237	0	0
T150	12470	22	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2229	0	0
T92	4066	24	0	0
T93	7482	24	0	0
T103	2612	7	0	0
T105	10451	37	0	0
T119	23110	81	0	0
T121	12707	45	0	0
T128	4326	10	0	0
T148	1913	9	0	0
T149	72274	229	0	0
T150	12470	46	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2179	0	0
T92	4066	18	0	0
T93	7482	23	0	0
T103	2612	3	0	0
T105	10451	49	0	0
T119	23110	81	0	0
T121	12707	28	0	0
T128	4326	9	0	0
T148	1913	1	0	0
T149	72274	176	0	0
T150	12470	91	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2324	0	0
T92	4066	14	0	0
T93	7482	17	0	0
T103	2612	7	0	0
T105	10451	43	0	0
T119	23110	72	0	0
T121	12707	31	0	0
T128	4326	9	0	0
T148	1913	5	0	0
T149	72274	219	0	0
T150	12470	50	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2089	0	0
T92	4066	21	0	0
T93	7482	21	0	0
T103	2612	7	0	0
T105	10451	48	0	0
T119	23110	76	0	0
T121	12707	39	0	0
T128	4326	5	0	0
T149	72274	220	0	0
T150	12470	28	0	0
T151	27003	216	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2328	0	0
T92	4066	14	0	0
T93	7482	29	0	0
T103	2612	13	0	0
T105	10451	45	0	0
T119	23110	90	0	0
T121	12707	28	0	0
T128	4326	12	0	0
T148	1913	2	0	0
T149	72274	230	0	0
T150	12470	70	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2244	0	0
T92	4066	12	0	0
T93	7482	32	0	0
T103	2612	12	0	0
T105	10451	58	0	0
T119	23110	86	0	0
T121	12707	39	0	0
T128	4326	2	0	0
T148	1913	3	0	0
T149	72274	180	0	0
T150	12470	58	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646338836	2339	0	0
T92	4066	20	0	0
T93	7482	36	0	0
T103	2612	8	0	0
T105	10451	34	0	0
T119	23110	87	0	0
T121	12707	52	0	0
T128	4326	13	0	0
T148	1913	6	0	0
T149	72274	241	0	0
T150	12470	46	0	0