Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43200544	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

51557676

1

T1

195

T2

443

T3

432

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51389095	1			T1	116		T2	305		T3	303
values[0x0]	21002915	1			T1	59		T2	143		T3	136
values[0x1]	22366210	1			T1	58		T2	142		T3	147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33550735	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

61207485

1

T1

200

T2

474

T3

471

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1119830	1			T2	3		T3	1		T4	8
valid_sources[0x01]	283050	1			T1	1		T2	2		T3	3
valid_sources[0x02]	300875	1			T4	11		T12	8		T15	2
valid_sources[0x03]	1177592	1			T2	2		T3	4		T4	15
valid_sources[0x04]	294814	1			T2	3		T3	1		T4	12
valid_sources[0x05]	308914	1			T1	2		T2	2		T4	4
valid_sources[0x06]	287862	1			T3	5		T4	13		T15	3
valid_sources[0x07]	349828	1			T1	2		T2	2		T3	3
valid_sources[0x08]	286073	1			T1	4		T2	2		T3	2
valid_sources[0x09]	454362	1			T1	1		T2	1		T3	2
valid_sources[0x0a]	285780	1			T1	1		T2	2		T4	9
valid_sources[0x0b]	288447	1			T1	1		T2	5		T3	3
valid_sources[0x0c]	301492	1			T1	1		T2	6		T3	2
valid_sources[0x0d]	288497	1			T2	2		T3	1		T4	8
valid_sources[0x0e]	285591	1			T2	3		T3	6		T4	11
valid_sources[0x0f]	283131	1			T1	1		T2	1		T3	4
valid_sources[0x10]	563930	1			T1	3		T2	5		T3	1
valid_sources[0x11]	285219	1			T2	3		T3	2		T4	14
valid_sources[0x12]	285548	1			T1	1		T2	5		T3	1
valid_sources[0x13]	288376	1			T2	2		T3	1		T4	9
valid_sources[0x14]	286490	1			T1	1		T4	12		T12	12
valid_sources[0x15]	285903	1			T1	2		T3	5		T4	13
valid_sources[0x16]	289397	1			T1	1		T2	5		T4	8
valid_sources[0x17]	286127	1			T2	2		T3	2		T4	10
valid_sources[0x18]	386121	1			T2	1		T4	13		T12	11
valid_sources[0x19]	331871	1			T1	1		T2	2		T3	2
valid_sources[0x1a]	572466	1			T1	1		T2	4		T4	10
valid_sources[0x1b]	285050	1			T2	2		T3	7		T4	9
valid_sources[0x1c]	288075	1			T2	3		T4	10		T13	7
valid_sources[0x1d]	1304146	1			T2	6		T3	3		T4	14
valid_sources[0x1e]	289067	1			T3	4		T4	17		T13	3
valid_sources[0x1f]	305950	1			T1	3		T2	4		T3	3
valid_sources[0x20]	286712	1			T2	2		T3	4		T4	11
valid_sources[0x21]	286668	1			T2	1		T3	2		T4	16
valid_sources[0x22]	343060	1			T2	2		T3	1		T4	17
valid_sources[0x23]	633911	1			T2	5		T3	1		T4	6
valid_sources[0x24]	283386	1			T3	3		T4	5		T12	11
valid_sources[0x25]	333376	1			T2	1		T3	3		T4	7
valid_sources[0x26]	287304	1			T1	2		T2	1		T3	5
valid_sources[0x27]	287927	1			T3	4		T4	12		T12	19
valid_sources[0x28]	378443	1			T2	1		T4	6		T13	6
valid_sources[0x29]	284920	1			T1	1		T2	3		T3	1
valid_sources[0x2a]	450627	1			T1	2		T2	3		T4	19
valid_sources[0x2b]	282467	1			T2	4		T4	15		T12	30
valid_sources[0x2c]	1289669	1			T1	2		T2	2		T3	1
valid_sources[0x2d]	286598	1			T1	1		T2	3		T3	2
valid_sources[0x2e]	288796	1			T1	1		T2	2		T3	7
valid_sources[0x2f]	286324	1			T1	2		T2	4		T3	3
valid_sources[0x30]	283091	1			T2	2		T3	1		T4	14
valid_sources[0x31]	285824	1			T2	2		T3	1		T4	7
valid_sources[0x32]	349361	1			T2	3		T3	3		T4	8
valid_sources[0x33]	308355	1			T3	3		T4	5		T12	29
valid_sources[0x34]	284578	1			T1	1		T2	1		T3	1
valid_sources[0x35]	662539	1			T2	5		T4	8		T15	2
valid_sources[0x36]	285221	1			T2	5		T3	4		T4	11
valid_sources[0x37]	331909	1			T2	4		T3	6		T4	12
valid_sources[0x38]	289863	1			T1	2		T2	3		T3	1
valid_sources[0x39]	299803	1			T2	1		T3	2		T4	11
valid_sources[0x3a]	374199	1			T2	4		T3	7		T4	15
valid_sources[0x3b]	910626	1			T2	4		T3	8		T4	11
valid_sources[0x3c]	286087	1			T1	1		T2	1		T3	1
valid_sources[0x3d]	283609	1			T2	1		T4	14		T12	9
valid_sources[0x3e]	287669	1			T2	2		T3	7		T4	21
valid_sources[0x3f]	288937	1			T1	2		T2	3		T4	9
valid_sources[0x40]	347311	1			T1	1		T2	2		T3	2
valid_sources[0x41]	398204	1			T2	1		T3	3		T4	6
valid_sources[0x42]	285949	1			T1	5		T2	2		T3	2
valid_sources[0x43]	288512	1			T1	1		T2	3		T3	4
valid_sources[0x44]	286238	1			T1	3		T2	2		T3	4
valid_sources[0x45]	287959	1			T1	1		T2	4		T3	5
valid_sources[0x46]	285343	1			T1	1		T3	2		T4	13
valid_sources[0x47]	330655	1			T2	3		T4	8		T13	1
valid_sources[0x48]	746666	1			T2	4		T3	1		T4	10
valid_sources[0x49]	300834	1			T1	2		T2	1		T3	3
valid_sources[0x4a]	289570	1			T1	1		T2	3		T3	2
valid_sources[0x4b]	311242	1			T1	2		T2	3		T3	2
valid_sources[0x4c]	327175	1			T2	1		T3	2		T4	10
valid_sources[0x4d]	285499	1			T1	1		T3	3		T4	5
valid_sources[0x4e]	288085	1			T1	1		T2	6		T3	3
valid_sources[0x4f]	284708	1			T1	1		T2	4		T3	2
valid_sources[0x50]	286408	1			T1	1		T2	3		T3	7
valid_sources[0x51]	367701	1			T2	2		T3	3		T4	8
valid_sources[0x52]	285244	1			T2	3		T3	2		T4	10
valid_sources[0x53]	450088	1			T2	1		T3	2		T4	13
valid_sources[0x54]	287352	1			T1	2		T2	2		T4	15
valid_sources[0x55]	288383	1			T1	1		T2	2		T3	3
valid_sources[0x56]	288791	1			T2	1		T3	4		T4	9
valid_sources[0x57]	286010	1			T2	3		T3	4		T4	16
valid_sources[0x58]	408006	1			T2	4		T3	5		T4	12
valid_sources[0x59]	290289	1			T1	1		T2	2		T3	3
valid_sources[0x5a]	282730	1			T3	5		T4	17		T15	3
valid_sources[0x5b]	286993	1			T1	1		T2	3		T4	15
valid_sources[0x5c]	290371	1			T1	1		T2	2		T3	5
valid_sources[0x5d]	284982	1			T3	1		T4	8		T13	2
valid_sources[0x5e]	283337	1			T1	1		T3	1		T4	8
valid_sources[0x5f]	283742	1			T1	1		T2	1		T4	10
valid_sources[0x60]	290974	1			T1	2		T2	2		T4	13
valid_sources[0x61]	456681	1			T2	3		T3	4		T4	6
valid_sources[0x62]	283997	1			T1	1		T3	1		T4	10
valid_sources[0x63]	287016	1			T1	1		T2	2		T4	14
valid_sources[0x64]	282352	1			T1	2		T2	2		T3	3
valid_sources[0x65]	289004	1			T1	2		T2	1		T4	6
valid_sources[0x66]	287259	1			T1	2		T2	5		T3	5
valid_sources[0x67]	396911	1			T1	1		T2	2		T4	4
valid_sources[0x68]	285510	1			T3	1		T4	12		T15	7
valid_sources[0x69]	282137	1			T2	4		T4	7		T13	9
valid_sources[0x6a]	287329	1			T1	2		T2	3		T3	5
valid_sources[0x6b]	855661	1			T1	3		T2	3		T3	1
valid_sources[0x6c]	422270	1			T1	1		T2	1		T3	1
valid_sources[0x6d]	287933	1			T1	1		T2	5		T3	3
valid_sources[0x6e]	306127	1			T2	3		T4	4		T12	16
valid_sources[0x6f]	288546	1			T3	6		T4	11		T12	11
valid_sources[0x70]	283719	1			T1	2		T2	1		T3	8
valid_sources[0x71]	463900	1			T2	3		T3	4		T4	7
valid_sources[0x72]	282433	1			T1	1		T2	1		T3	7
valid_sources[0x73]	288847	1			T2	2		T3	2		T4	26
valid_sources[0x74]	286243	1			T2	3		T4	16		T15	6
valid_sources[0x75]	286744	1			T1	2		T2	2		T3	1
valid_sources[0x76]	285537	1			T1	2		T2	8		T4	12
valid_sources[0x77]	284066	1			T1	2		T2	2		T3	3
valid_sources[0x78]	326038	1			T1	1		T2	5		T3	1
valid_sources[0x79]	286552	1			T2	6		T4	7		T13	2
valid_sources[0x7a]	303440	1			T1	1		T2	2		T4	7
valid_sources[0x7b]	310383	1			T1	3		T2	3		T3	6
valid_sources[0x7c]	282598	1			T2	5		T4	11		T12	43
valid_sources[0x7d]	287913	1			T1	1		T2	5		T3	8
valid_sources[0x7e]	523578	1			T1	2		T2	2		T4	20
valid_sources[0x7f]	284730	1			T2	1		T3	1		T4	12
valid_sources[0x80]	287206	1			T2	3		T3	4		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24885188

1

T1

94

T2

209

T3

215

values[0x0]

all_enables

biggest_size

14036584

1

T1

50

T2

121

T3

109

values[0x1]

all_enables

biggest_size

12635904

1

T1

51

T2

113

T3

108