Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43262784

1

T1

38

T2

147

T3

154

full_word

51561570

1

T1

195

T2

443

T3

432

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	94824034	1			T1	233		T2	590		T3	586
auto[TlIntgErrCmd]	98	1			T118	6		T119	3		T120	7
auto[TlIntgErrData]	112	1			T118	9		T119	5		T120	7
auto[TlIntgErrBoth]	110	1			T118	5		T119	2		T120	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51403119

1

T1

116

T2

305

T3

303

auto[1]

43421235

1

T1

117

T2

285

T3

283

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26516776	1			T1	22		T2	96		T3	88
auto[TlIntgErrNone]	partial	auto[1]	16745719	1			T1	16		T2	51		T3	66
auto[TlIntgErrNone]	full_word	auto[0]	24886203	1			T1	94		T2	209		T3	215
auto[TlIntgErrNone]	full_word	auto[1]	26675336	1			T1	101		T2	234		T3	217
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T118	2		T119	1		T120	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T118	4		T119	1		T120	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T119	1		T183	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T179	1		T184	1		T181	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T118	4		T119	2		T120	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T118	5		T119	2		T120	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T184	1		T185	1		T186	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T119	1		T120	1		T184	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T118	1		T120	1		T179	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T118	4		T119	2		T120	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T120	1		T185	1		T186	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T120	1		T184	1		T180	1