Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	599643179	11587	0	0
entropy_period_rd_A	599643179	1040	0	0
intr_enable_rd_A	599643179	1525	0	0
prefix_0_rd_A	599643179	858	0	0
prefix_10_rd_A	599643179	879	0	0
prefix_1_rd_A	599643179	913	0	0
prefix_2_rd_A	599643179	788	0	0
prefix_3_rd_A	599643179	852	0	0
prefix_4_rd_A	599643179	789	0	0
prefix_5_rd_A	599643179	817	0	0
prefix_6_rd_A	599643179	892	0	0
prefix_7_rd_A	599643179	825	0	0
prefix_8_rd_A	599643179	899	0	0
prefix_9_rd_A	599643179	712	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	11587	0	0
T24	142178	0	0	0
T25	109801	0	0	0
T32	279117	3810	0	0
T39	146567	0	0	0
T40	0	1822	0	0
T59	0	1337	0	0
T69	2019	0	0	0
T72	126875	0	0	0
T86	36077	0	0	0
T87	0	1430	0	0
T118	0	2	0	0
T119	0	1	0	0
T124	0	86	0	0
T125	0	3	0	0
T126	0	196	0	0
T127	0	30	0	0
T129	37442	0	0	0
T130	87359	0	0	0
T131	23331	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	1040	0	0
T36	123289	0	0	0
T40	189263	12	0	0
T59	0	22	0	0
T115	131465	0	0	0
T119	0	56	0	0
T122	0	11	0	0
T125	0	15	0	0
T128	0	2	0	0
T144	0	6	0	0
T145	0	5	0	0
T146	0	13	0	0
T147	0	28	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	1525	0	0
T36	123289	0	0	0
T40	189263	14	0	0
T59	0	23	0	0
T101	0	14	0	0
T115	131465	0	0	0
T119	0	91	0	0
T121	0	7	0	0
T122	0	14	0	0
T125	0	33	0	0
T144	0	26	0	0
T145	0	51	0	0
T146	0	13	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	858	0	0
T36	123289	0	0	0
T40	189263	18	0	0
T59	0	12	0	0
T101	0	11	0	0
T115	131465	0	0	0
T119	0	37	0	0
T122	0	13	0	0
T125	0	17	0	0
T144	0	3	0	0
T145	0	13	0	0
T146	0	15	0	0
T147	0	32	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	879	0	0
T36	123289	0	0	0
T40	189263	16	0	0
T59	0	14	0	0
T115	131465	0	0	0
T119	0	28	0	0
T122	0	14	0	0
T125	0	12	0	0
T144	0	9	0	0
T145	0	37	0	0
T146	0	12	0	0
T147	0	46	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0
T155	0	19	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	913	0	0
T36	123289	0	0	0
T40	189263	25	0	0
T59	0	19	0	0
T101	0	11	0	0
T115	131465	0	0	0
T119	0	44	0	0
T122	0	9	0	0
T125	0	13	0	0
T144	0	14	0	0
T145	0	34	0	0
T146	0	8	0	0
T147	0	47	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	788	0	0
T36	123289	0	0	0
T40	189263	17	0	0
T59	0	29	0	0
T101	0	2	0	0
T115	131465	0	0	0
T119	0	39	0	0
T122	0	8	0	0
T125	0	16	0	0
T144	0	5	0	0
T145	0	26	0	0
T146	0	10	0	0
T147	0	11	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	852	0	0
T36	123289	0	0	0
T40	189263	9	0	0
T59	0	24	0	0
T101	0	1	0	0
T115	131465	0	0	0
T119	0	49	0	0
T122	0	9	0	0
T125	0	10	0	0
T144	0	13	0	0
T145	0	3	0	0
T146	0	14	0	0
T147	0	35	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	789	0	0
T36	123289	0	0	0
T40	189263	12	0	0
T59	0	26	0	0
T101	0	7	0	0
T115	131465	0	0	0
T119	0	38	0	0
T122	0	8	0	0
T125	0	18	0	0
T144	0	9	0	0
T145	0	42	0	0
T146	0	4	0	0
T147	0	16	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	817	0	0
T36	123289	0	0	0
T40	189263	4	0	0
T59	0	26	0	0
T101	0	7	0	0
T115	131465	0	0	0
T119	0	37	0	0
T122	0	6	0	0
T125	0	18	0	0
T144	0	7	0	0
T145	0	27	0	0
T146	0	9	0	0
T147	0	13	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	892	0	0
T36	123289	0	0	0
T40	189263	12	0	0
T59	0	18	0	0
T101	0	2	0	0
T115	131465	0	0	0
T119	0	35	0	0
T122	0	11	0	0
T125	0	18	0	0
T144	0	10	0	0
T145	0	1	0	0
T146	0	8	0	0
T147	0	56	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	825	0	0
T36	123289	0	0	0
T40	189263	15	0	0
T59	0	23	0	0
T101	0	14	0	0
T115	131465	0	0	0
T119	0	35	0	0
T122	0	6	0	0
T125	0	20	0	0
T144	0	11	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	35	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	899	0	0
T36	123289	0	0	0
T40	189263	16	0	0
T59	0	17	0	0
T101	0	11	0	0
T115	131465	0	0	0
T119	0	53	0	0
T122	0	10	0	0
T125	0	16	0	0
T144	0	13	0	0
T145	0	42	0	0
T146	0	8	0	0
T147	0	22	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599643179	712	0	0
T36	123289	0	0	0
T40	189263	6	0	0
T59	0	12	0	0
T101	0	4	0	0
T115	131465	0	0	0
T119	0	49	0	0
T122	0	11	0	0
T125	0	14	0	0
T144	0	7	0	0
T145	0	25	0	0
T146	0	6	0	0
T147	0	14	0	0
T148	1373	0	0	0
T149	82525	0	0	0
T150	237969	0	0	0
T151	271382	0	0	0
T152	437081	0	0	0
T153	154457	0	0	0
T154	55662	0	0	0