Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49568736	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

55602471

1

T1

424

T2

439

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56469775	1			T1	347		T2	309		T3	1
values[0x0]	23552401	1			T1	154		T2	150		T3	7
values[0x1]	25149031	1			T1	171		T2	138		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38501582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66669625

1

T1

477

T2

472

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	314714	1			T2	3		T3	2		T4	2
valid_sources[0x01]	363844	1			T4	1		T5	5		T13	1
valid_sources[0x02]	852982	1			T13	2		T15	2		T17	6
valid_sources[0x03]	315388	1			T1	3		T2	2		T4	1
valid_sources[0x04]	320134	1			T5	3		T13	2		T15	1
valid_sources[0x05]	314862	1			T2	1		T5	3		T13	2
valid_sources[0x06]	315668	1			T2	10		T5	1		T13	2
valid_sources[0x07]	311425	1			T2	3		T4	1		T5	7
valid_sources[0x08]	324143	1			T4	1		T5	1		T14	11
valid_sources[0x09]	374213	1			T2	2		T3	2		T5	2
valid_sources[0x0a]	313218	1			T2	3		T4	1		T5	3
valid_sources[0x0b]	315366	1			T4	2		T5	2		T13	2
valid_sources[0x0c]	312404	1			T1	2		T2	2		T3	1
valid_sources[0x0d]	1316922	1			T2	1		T4	1		T5	4
valid_sources[0x0e]	313935	1			T1	3		T5	3		T12	1
valid_sources[0x0f]	313607	1			T4	1		T5	2		T13	2
valid_sources[0x10]	315530	1			T1	7		T2	1		T4	1
valid_sources[0x11]	315889	1			T1	1		T2	15		T4	2
valid_sources[0x12]	404352	1			T1	4		T2	10		T5	3
valid_sources[0x13]	316397	1			T1	37		T2	8		T3	1
valid_sources[0x14]	321282	1			T1	3		T2	8		T4	1
valid_sources[0x15]	410277	1			T2	2		T5	3		T13	2
valid_sources[0x16]	312548	1			T2	3		T5	2		T12	21
valid_sources[0x17]	313112	1			T1	24		T5	4		T13	3
valid_sources[0x18]	418373	1			T1	2		T4	2		T5	3
valid_sources[0x19]	311801	1			T3	1		T5	4		T13	1
valid_sources[0x1a]	350840	1			T4	1		T5	1		T14	2
valid_sources[0x1b]	315107	1			T2	7		T4	2		T5	9
valid_sources[0x1c]	316865	1			T1	2		T2	7		T5	4
valid_sources[0x1d]	314789	1			T2	4		T13	2		T14	4
valid_sources[0x1e]	400679	1			T5	3		T13	2		T14	1
valid_sources[0x1f]	314417	1			T2	1		T4	1		T5	1
valid_sources[0x20]	312743	1			T4	1		T14	4		T15	1
valid_sources[0x21]	315456	1			T2	1		T4	2		T5	2
valid_sources[0x22]	324821	1			T2	1		T4	2		T5	3
valid_sources[0x23]	311181	1			T1	7		T2	6		T5	8
valid_sources[0x24]	317053	1			T2	1		T5	5		T13	1
valid_sources[0x25]	320455	1			T1	2		T2	1		T4	1
valid_sources[0x26]	1369602	1			T1	5		T2	5		T4	2
valid_sources[0x27]	313062	1			T2	4		T4	1		T5	5
valid_sources[0x28]	314838	1			T1	2		T5	4		T14	2
valid_sources[0x29]	554926	1			T2	3		T4	3		T5	3
valid_sources[0x2a]	314533	1			T1	3		T2	2		T5	3
valid_sources[0x2b]	328751	1			T1	7		T4	1		T5	1
valid_sources[0x2c]	318795	1			T2	1		T4	3		T5	2
valid_sources[0x2d]	314339	1			T2	2		T5	4		T13	1
valid_sources[0x2e]	318532	1			T4	1		T5	1		T12	14
valid_sources[0x2f]	312428	1			T2	1		T4	3		T5	5
valid_sources[0x30]	316472	1			T2	3		T4	4		T5	5
valid_sources[0x31]	321128	1			T1	6		T5	4		T13	1
valid_sources[0x32]	315462	1			T4	1		T5	1		T13	1
valid_sources[0x33]	384373	1			T1	1		T2	1		T5	7
valid_sources[0x34]	320790	1			T13	6456		T14	1		T17	4
valid_sources[0x35]	318560	1			T1	8		T4	1		T5	2
valid_sources[0x36]	317998	1			T1	6		T5	2		T12	21
valid_sources[0x37]	311183	1			T1	14		T4	1		T13	1
valid_sources[0x38]	313659	1			T1	4		T4	2		T5	5
valid_sources[0x39]	541976	1			T4	1		T5	3		T13	1
valid_sources[0x3a]	599767	1			T1	2		T4	1		T5	5
valid_sources[0x3b]	959225	1			T1	3		T2	4		T5	7
valid_sources[0x3c]	317491	1			T1	8		T4	1		T5	1
valid_sources[0x3d]	504006	1			T2	12		T4	1		T5	4
valid_sources[0x3e]	1607307	1			T1	5		T2	3		T4	1
valid_sources[0x3f]	460382	1			T5	4		T13	1		T14	3
valid_sources[0x40]	316753	1			T2	5		T4	3		T5	3
valid_sources[0x41]	322828	1			T1	1		T2	1		T4	1
valid_sources[0x42]	317541	1			T5	1		T15	2		T17	1
valid_sources[0x43]	964103	1			T12	42		T13	2		T14	8
valid_sources[0x44]	537714	1			T5	4		T13	2		T14	2
valid_sources[0x45]	317940	1			T2	4		T5	10		T17	3
valid_sources[0x46]	314067	1			T4	3		T5	8		T14	1
valid_sources[0x47]	316573	1			T1	1		T5	8		T13	1
valid_sources[0x48]	311024	1			T4	1		T5	7		T12	45
valid_sources[0x49]	337489	1			T4	1		T5	2		T14	3
valid_sources[0x4a]	316630	1			T1	6		T2	10		T4	1
valid_sources[0x4b]	534323	1			T2	2		T5	2		T12	14
valid_sources[0x4c]	318435	1			T1	8		T4	2		T5	10
valid_sources[0x4d]	900865	1			T2	6		T3	1		T4	4
valid_sources[0x4e]	314082	1			T1	3		T2	2		T4	1
valid_sources[0x4f]	1169057	1			T1	17		T2	6		T5	1
valid_sources[0x50]	312959	1			T1	12		T5	6		T13	2
valid_sources[0x51]	475569	1			T1	6		T5	2		T14	4
valid_sources[0x52]	321143	1			T1	1		T5	8		T13	1
valid_sources[0x53]	315205	1			T1	2		T2	6		T4	1
valid_sources[0x54]	312616	1			T1	8		T4	1		T5	2
valid_sources[0x55]	315308	1			T1	3		T5	5		T13	1
valid_sources[0x56]	382586	1			T1	6		T4	1		T5	8
valid_sources[0x57]	316144	1			T1	10		T5	1		T13	1
valid_sources[0x58]	315552	1			T3	1		T4	2		T5	1
valid_sources[0x59]	316852	1			T2	2		T3	1		T5	9
valid_sources[0x5a]	313285	1			T1	2		T2	7		T4	2
valid_sources[0x5b]	314119	1			T5	7		T14	2		T6	70
valid_sources[0x5c]	878828	1			T1	3		T2	2		T4	1
valid_sources[0x5d]	314010	1			T4	1		T5	1		T15	2
valid_sources[0x5e]	311845	1			T2	5		T4	1		T5	1
valid_sources[0x5f]	400731	1			T4	2		T5	3		T15	1
valid_sources[0x60]	952737	1			T4	2		T5	4		T12	12
valid_sources[0x61]	315703	1			T1	3		T4	2		T5	3
valid_sources[0x62]	315428	1			T4	3		T5	3		T13	2
valid_sources[0x63]	439397	1			T5	2		T13	1		T14	7
valid_sources[0x64]	329627	1			T2	6		T4	1		T5	2
valid_sources[0x65]	312359	1			T1	4		T4	2		T14	4
valid_sources[0x66]	754476	1			T1	4		T4	2		T5	5
valid_sources[0x67]	312880	1			T1	8		T2	1		T5	1
valid_sources[0x68]	315156	1			T2	18		T4	1		T5	4
valid_sources[0x69]	329924	1			T1	3		T2	2		T5	4
valid_sources[0x6a]	1202218	1			T1	2		T5	2		T13	1
valid_sources[0x6b]	572084	1			T2	11		T5	5		T17	3
valid_sources[0x6c]	314989	1			T1	2		T4	3		T5	8
valid_sources[0x6d]	313984	1			T1	7		T5	2		T13	1
valid_sources[0x6e]	312267	1			T1	9		T2	2		T4	1
valid_sources[0x6f]	315813	1			T2	11		T4	2		T5	1
valid_sources[0x70]	314046	1			T1	1		T2	3		T4	1
valid_sources[0x71]	313539	1			T1	1		T5	2		T14	2
valid_sources[0x72]	315792	1			T1	14		T5	9		T13	1
valid_sources[0x73]	675933	1			T1	5		T2	2		T5	1
valid_sources[0x74]	924904	1			T1	4		T4	4		T5	5
valid_sources[0x75]	332363	1			T2	3		T4	3		T5	6
valid_sources[0x76]	315676	1			T2	2		T4	1		T5	3
valid_sources[0x77]	349392	1			T4	1		T5	1		T14	3
valid_sources[0x78]	317238	1			T5	1		T13	2		T14	4
valid_sources[0x79]	316897	1			T3	1		T5	13		T14	3
valid_sources[0x7a]	314210	1			T1	2		T2	1		T4	2
valid_sources[0x7b]	486020	1			T1	20		T2	1		T4	1
valid_sources[0x7c]	312988	1			T3	1		T4	1		T5	3
valid_sources[0x7d]	320804	1			T1	35		T4	1		T5	3
valid_sources[0x7e]	338493	1			T2	3		T4	3		T5	3
valid_sources[0x7f]	318526	1			T2	12		T4	1		T5	2
valid_sources[0x80]	332932	1			T1	10		T3	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26164789

1

T1

221

T2

205

T3

1

values[0x0]

all_enables

biggest_size

15521332

1

T1

105

T2

124

T3

2

values[0x1]

all_enables

biggest_size

13916350

1

T1

98

T2

110

T3

2