Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

49657394

1

T1

248

T2

158

T3

18

full_word

55607992

1

T1

424

T2

439

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	105265106	1			T1	672		T2	597		T3	23
auto[TlIntgErrCmd]	91	1			T108	5		T109	6		T110	3
auto[TlIntgErrData]	96	1			T108	2		T109	3		T110	6
auto[TlIntgErrBoth]	93	1			T108	3		T109	1		T110	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56489951

1

T1

347

T2

309

T3

1

auto[1]

48775435

1

T1

325

T2

288

T3

22

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	30323532	1			T1	126		T2	104		T4	7
auto[TlIntgErrNone]	partial	auto[1]	19333603	1			T1	122		T2	54		T3	18
auto[TlIntgErrNone]	full_word	auto[0]	26166293	1			T1	221		T2	205		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	29441678	1			T1	203		T2	234		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T108	3		T109	2		T110	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T108	2		T109	4		T110	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T174	1		T172	1		T175	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T176	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1			T108	1		T109	1		T171	5
auto[TlIntgErrData]	partial	auto[1]	52	1			T108	1		T109	2		T110	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T110	1		T171	1		T177	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T173	1		T178	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T108	2		T110	5		T171	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T108	1		T110	3		T171	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T110	3		T179	1		T180	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T109	1		T170	1		T179	1