Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	682925173	61477216	0	0
DataKnown_AKnownEnable	682925173	682744859	0	0
DepthKnown_A	682925173	682744859	0	0
RvalidKnown_A	682925173	682744859	0	0
WreadyKnown_A	682925173	682744859	0	0
gen_passthru_fifo.paramCheckPass	883	883	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	61477216	0	0
T1	2648	421	0	0
T2	5465	365	0	0
T3	933	23	0	0
T4	2633	121	0	0
T5	11640	479	0	0
T12	117788	982	0	0
T13	61338	3305	0	0
T14	5366	398	0	0
T15	36858	5409	0	0
T16	238280	1371	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	682744859	0	0
T1	2648	2589	0	0
T2	5465	5367	0	0
T3	933	874	0	0
T4	2633	2509	0	0
T5	11640	11560	0	0
T12	117788	117728	0	0
T13	61338	61258	0	0
T14	5366	5291	0	0
T15	36858	36770	0	0
T16	238280	238218	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	682744859	0	0
T1	2648	2589	0	0
T2	5465	5367	0	0
T3	933	874	0	0
T4	2633	2509	0	0
T5	11640	11560	0	0
T12	117788	117728	0	0
T13	61338	61258	0	0
T14	5366	5291	0	0
T15	36858	36770	0	0
T16	238280	238218	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	682744859	0	0
T1	2648	2589	0	0
T2	5465	5367	0	0
T3	933	874	0	0
T4	2633	2509	0	0
T5	11640	11560	0	0
T12	117788	117728	0	0
T13	61338	61258	0	0
T14	5366	5291	0	0
T15	36858	36770	0	0
T16	238280	238218	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	682744859	0	0
T1	2648	2589	0	0
T2	5465	5367	0	0
T3	933	874	0	0
T4	2633	2509	0	0
T5	11640	11560	0	0
T12	117788	117728	0	0
T13	61338	61258	0	0
T14	5366	5291	0	0
T15	36858	36770	0	0
T16	238280	238218	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	682925173	118459150	0	0
DataKnown_AKnownEnable	682925173	682744859	0	0
DepthKnown_A	682925173	682744859	0	0
RvalidKnown_A	682925173	682744859	0	0
WreadyKnown_A	682925173	682744859	0	0
gen_passthru_fifo.paramCheckPass	883	883	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	118459150	0	0
T1	2648	421	0	0
T2	5465	365	0	0
T3	933	23	0	0
T4	2633	121	0	0
T5	11640	2120	0	0
T12	117788	982	0	0
T13	61338	10204	0	0
T14	5366	398	0	0
T15	36858	5409	0	0
T16	238280	1371	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	682744859	0	0
T1	2648	2589	0	0
T2	5465	5367	0	0
T3	933	874	0	0
T4	2633	2509	0	0
T5	11640	11560	0	0
T12	117788	117728	0	0
T13	61338	61258	0	0
T14	5366	5291	0	0
T15	36858	36770	0	0
T16	238280	238218	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	682744859	0	0
T1	2648	2589	0	0
T2	5465	5367	0	0
T3	933	874	0	0
T4	2633	2509	0	0
T5	11640	11560	0	0
T12	117788	117728	0	0
T13	61338	61258	0	0
T14	5366	5291	0	0
T15	36858	36770	0	0
T16	238280	238218	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	682744859	0	0
T1	2648	2589	0	0
T2	5465	5367	0	0
T3	933	874	0	0
T4	2633	2509	0	0
T5	11640	11560	0	0
T12	117788	117728	0	0
T13	61338	61258	0	0
T14	5366	5291	0	0
T15	36858	36770	0	0
T16	238280	238218	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	682744859	0	0
T1	2648	2589	0	0
T2	5465	5367	0	0
T3	933	874	0	0
T4	2633	2509	0	0
T5	11640	11560	0	0
T12	117788	117728	0	0
T13	61338	61258	0	0
T14	5366	5291	0	0
T15	36858	36770	0	0
T16	238280	238218	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	883	883	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0