Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	682925173	15924	0	0
entropy_period_rd_A	682925173	2541	0	0
intr_enable_rd_A	682925173	3086	0	0
prefix_0_rd_A	682925173	2574	0	0
prefix_10_rd_A	682925173	2549	0	0
prefix_1_rd_A	682925173	2550	0	0
prefix_2_rd_A	682925173	2524	0	0
prefix_3_rd_A	682925173	2561	0	0
prefix_4_rd_A	682925173	2485	0	0
prefix_5_rd_A	682925173	2448	0	0
prefix_6_rd_A	682925173	2590	0	0
prefix_7_rd_A	682925173	2513	0	0
prefix_8_rd_A	682925173	2514	0	0
prefix_9_rd_A	682925173	2469	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	15924	0	0
T40	0	3940	0	0
T56	150386	1210	0	0
T57	0	3982	0	0
T58	0	2566	0	0
T64	2314	0	0	0
T67	130293	0	0	0
T89	0	1059	0	0
T108	0	1	0	0
T109	0	1	0	0
T114	0	169	0	0
T115	0	1	0	0
T116	0	115	0	0
T119	264617	0	0	0
T120	48893	0	0	0
T121	50533	0	0	0
T122	981646	0	0	0
T123	369051	0	0	0
T124	42985	0	0	0
T125	1192	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2541	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	20	0	0
T91	0	80	0	0
T95	0	10	0	0
T109	0	47	0	0
T115	0	8	0	0
T117	0	28	0	0
T140	737485	0	0	0
T143	0	350	0	0
T144	0	13	0	0
T145	0	217	0	0
T146	0	3	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	3086	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	10	0	0
T91	0	93	0	0
T95	0	10	0	0
T109	0	51	0	0
T113	0	7	0	0
T115	0	16	0	0
T117	0	22	0	0
T140	737485	0	0	0
T143	0	421	0	0
T145	0	203	0	0
T146	0	14	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2574	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	22	0	0
T91	0	64	0	0
T95	0	14	0	0
T96	0	3	0	0
T109	0	27	0	0
T115	0	9	0	0
T117	0	21	0	0
T140	737485	0	0	0
T143	0	429	0	0
T145	0	209	0	0
T146	0	4	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2549	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	21	0	0
T91	0	72	0	0
T95	0	9	0	0
T109	0	32	0	0
T115	0	8	0	0
T117	0	17	0	0
T140	737485	0	0	0
T143	0	417	0	0
T144	0	7	0	0
T145	0	195	0	0
T146	0	2	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2550	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	39	0	0
T91	0	57	0	0
T95	0	11	0	0
T96	0	3	0	0
T109	0	15	0	0
T115	0	7	0	0
T117	0	16	0	0
T140	737485	0	0	0
T143	0	452	0	0
T145	0	207	0	0
T146	0	1	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2524	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	25	0	0
T91	0	58	0	0
T95	0	21	0	0
T109	0	12	0	0
T115	0	1	0	0
T117	0	6	0	0
T140	737485	0	0	0
T143	0	434	0	0
T144	0	4	0	0
T145	0	218	0	0
T146	0	11	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2561	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	31	0	0
T91	0	60	0	0
T95	0	20	0	0
T109	0	43	0	0
T115	0	16	0	0
T117	0	17	0	0
T140	737485	0	0	0
T143	0	426	0	0
T144	0	3	0	0
T145	0	206	0	0
T146	0	7	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2485	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	14	0	0
T91	0	73	0	0
T95	0	23	0	0
T109	0	36	0	0
T115	0	11	0	0
T117	0	22	0	0
T140	737485	0	0	0
T143	0	449	0	0
T144	0	4	0	0
T145	0	196	0	0
T146	0	7	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2448	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	15	0	0
T91	0	52	0	0
T95	0	15	0	0
T109	0	11	0	0
T115	0	9	0	0
T117	0	11	0	0
T140	737485	0	0	0
T143	0	397	0	0
T144	0	3	0	0
T145	0	252	0	0
T146	0	11	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2590	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	25	0	0
T91	0	56	0	0
T95	0	26	0	0
T109	0	47	0	0
T115	0	7	0	0
T117	0	21	0	0
T140	737485	0	0	0
T143	0	415	0	0
T144	0	5	0	0
T145	0	269	0	0
T146	0	15	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2513	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	22	0	0
T91	0	52	0	0
T95	0	14	0	0
T96	0	12	0	0
T109	0	31	0	0
T115	0	9	0	0
T117	0	7	0	0
T140	737485	0	0	0
T143	0	434	0	0
T145	0	228	0	0
T146	0	4	0	0
T147	107657	0	0	0
T148	524541	0	0	0
T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2514	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	22	0	0
T91	0	55	0	0
T95	0	21	0	0
T96	0	9	0	0
T109	0	15	0	0
T115	0	8	0	0
T117	0	13	0	0
T140	737485	0	0	0
T143	0	386	0	0
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T149	291368	0	0	0
T150	11761	0	0	0
T151	124080	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682925173	2469	0	0
T27	870946	0	0	0
T46	412377	0	0	0
T81	547270	0	0	0
T89	312027	29	0	0
T91	0	68	0	0
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T109	0	40	0	0
T115	0	9	0	0
T117	0	11	0	0
T140	737485	0	0	0
T143	0	367	0	0
T144	0	5	0	0
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T146	0	3	0	0
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