| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 91.95 | 95.87 | 92.30 | 100.00 | 66.12 | 94.08 | 98.87 | 96.43 |
| T763 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.804301096 | Sep 24 09:10:43 PM UTC 24 | Sep 24 09:10:45 PM UTC 24 | 53030151 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3412357584 | Sep 24 09:10:41 PM UTC 24 | Sep 24 09:10:46 PM UTC 24 | 537403817 ps | ||
| T764 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3430972000 | Sep 24 09:10:43 PM UTC 24 | Sep 24 09:10:46 PM UTC 24 | 19187428 ps | ||
| T765 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3159949513 | Sep 24 09:10:42 PM UTC 24 | Sep 24 09:10:47 PM UTC 24 | 112042243 ps | ||
| T766 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3845606354 | Sep 24 09:10:43 PM UTC 24 | Sep 24 09:10:47 PM UTC 24 | 449001743 ps | ||
| T767 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3937475460 | Sep 24 09:10:43 PM UTC 24 | Sep 24 09:10:47 PM UTC 24 | 165465312 ps | ||
| T768 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.793911958 | Sep 24 09:10:45 PM UTC 24 | Sep 24 09:10:48 PM UTC 24 | 34563053 ps | ||
| T769 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.4224029194 | Sep 24 09:10:47 PM UTC 24 | Sep 24 09:10:49 PM UTC 24 | 22814797 ps | ||
| T770 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3422108046 | Sep 24 09:10:20 PM UTC 24 | Sep 24 09:10:50 PM UTC 24 | 1255531146 ps | ||
| T771 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1783145095 | Sep 24 09:10:47 PM UTC 24 | Sep 24 09:10:50 PM UTC 24 | 57608000 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3154034782 | Sep 24 09:10:48 PM UTC 24 | Sep 24 09:10:51 PM UTC 24 | 25040529 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2582886075 | Sep 24 09:10:47 PM UTC 24 | Sep 24 09:10:51 PM UTC 24 | 170527643 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1998754337 | Sep 24 09:10:43 PM UTC 24 | Sep 24 09:10:51 PM UTC 24 | 230250575 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1011576083 | Sep 24 09:10:48 PM UTC 24 | Sep 24 09:10:51 PM UTC 24 | 37778791 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.3459180630 | Sep 24 09:10:47 PM UTC 24 | Sep 24 09:10:51 PM UTC 24 | 125986673 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2215764038 | Sep 24 09:10:48 PM UTC 24 | Sep 24 09:10:51 PM UTC 24 | 76835473 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1443681176 | Sep 24 09:10:48 PM UTC 24 | Sep 24 09:10:53 PM UTC 24 | 111729705 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.4226331045 | Sep 24 09:10:52 PM UTC 24 | Sep 24 09:10:54 PM UTC 24 | 38528935 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.382249738 | Sep 24 09:10:52 PM UTC 24 | Sep 24 09:10:54 PM UTC 24 | 49927169 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3472513902 | Sep 24 09:10:52 PM UTC 24 | Sep 24 09:10:54 PM UTC 24 | 29070948 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3681182559 | Sep 24 09:10:50 PM UTC 24 | Sep 24 09:10:55 PM UTC 24 | 102412164 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2905491489 | Sep 24 09:10:52 PM UTC 24 | Sep 24 09:10:56 PM UTC 24 | 378058343 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1697984559 | Sep 24 09:10:52 PM UTC 24 | Sep 24 09:10:56 PM UTC 24 | 140367394 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2775882980 | Sep 24 09:10:52 PM UTC 24 | Sep 24 09:10:56 PM UTC 24 | 287388525 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1433343643 | Sep 24 09:10:52 PM UTC 24 | Sep 24 09:10:56 PM UTC 24 | 611724784 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.1310179764 | Sep 24 09:10:52 PM UTC 24 | Sep 24 09:10:58 PM UTC 24 | 217495123 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3256393329 | Sep 24 09:10:56 PM UTC 24 | Sep 24 09:10:58 PM UTC 24 | 16973596 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.2154294121 | Sep 24 09:10:56 PM UTC 24 | Sep 24 09:10:58 PM UTC 24 | 23738896 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1875264053 | Sep 24 09:10:56 PM UTC 24 | Sep 24 09:10:59 PM UTC 24 | 360633066 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2737385477 | Sep 24 09:10:54 PM UTC 24 | Sep 24 09:11:00 PM UTC 24 | 445556808 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.1719480332 | Sep 24 09:10:56 PM UTC 24 | Sep 24 09:11:01 PM UTC 24 | 820112867 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.120774351 | Sep 24 09:10:57 PM UTC 24 | Sep 24 09:11:01 PM UTC 24 | 33822410 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1086582983 | Sep 24 09:10:59 PM UTC 24 | Sep 24 09:11:01 PM UTC 24 | 16165679 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1300685808 | Sep 24 09:10:57 PM UTC 24 | Sep 24 09:11:02 PM UTC 24 | 129254666 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1203184806 | Sep 24 09:10:57 PM UTC 24 | Sep 24 09:11:02 PM UTC 24 | 78403227 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.2085509307 | Sep 24 09:11:00 PM UTC 24 | Sep 24 09:11:02 PM UTC 24 | 27524453 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3862743165 | Sep 24 09:10:57 PM UTC 24 | Sep 24 09:11:03 PM UTC 24 | 109918902 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3858169935 | Sep 24 09:10:59 PM UTC 24 | Sep 24 09:11:04 PM UTC 24 | 221414188 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3061604625 | Sep 24 09:11:00 PM UTC 24 | Sep 24 09:11:04 PM UTC 24 | 36448530 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1856888730 | Sep 24 09:11:01 PM UTC 24 | Sep 24 09:11:04 PM UTC 24 | 76956022 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1241587051 | Sep 24 09:11:01 PM UTC 24 | Sep 24 09:11:05 PM UTC 24 | 23286934 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.445007772 | Sep 24 09:11:02 PM UTC 24 | Sep 24 09:11:06 PM UTC 24 | 213739597 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2655018548 | Sep 24 09:11:03 PM UTC 24 | Sep 24 09:11:06 PM UTC 24 | 13852626 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.1990995038 | Sep 24 09:11:02 PM UTC 24 | Sep 24 09:11:06 PM UTC 24 | 304692877 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.256144169 | Sep 24 09:11:03 PM UTC 24 | Sep 24 09:11:06 PM UTC 24 | 29726889 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.4163823473 | Sep 24 09:11:04 PM UTC 24 | Sep 24 09:11:08 PM UTC 24 | 51961049 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.427193657 | Sep 24 09:11:03 PM UTC 24 | Sep 24 09:11:08 PM UTC 24 | 266071440 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1818166847 | Sep 24 09:11:06 PM UTC 24 | Sep 24 09:11:09 PM UTC 24 | 111148474 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2241714816 | Sep 24 09:11:22 PM UTC 24 | Sep 24 09:11:24 PM UTC 24 | 52475892 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.1938041007 | Sep 24 09:11:07 PM UTC 24 | Sep 24 09:11:09 PM UTC 24 | 44426268 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3382797201 | Sep 24 09:11:06 PM UTC 24 | Sep 24 09:11:09 PM UTC 24 | 66363694 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.1275445702 | Sep 24 09:11:07 PM UTC 24 | Sep 24 09:11:10 PM UTC 24 | 240846006 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3827013231 | Sep 24 09:11:07 PM UTC 24 | Sep 24 09:11:11 PM UTC 24 | 40396274 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.4120396518 | Sep 24 09:11:06 PM UTC 24 | Sep 24 09:11:11 PM UTC 24 | 170164011 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.861189579 | Sep 24 09:11:10 PM UTC 24 | Sep 24 09:11:12 PM UTC 24 | 26123166 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.864654065 | Sep 24 09:11:10 PM UTC 24 | Sep 24 09:11:13 PM UTC 24 | 91251661 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2741390163 | Sep 24 09:11:08 PM UTC 24 | Sep 24 09:11:14 PM UTC 24 | 339999519 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1062317970 | Sep 24 09:11:11 PM UTC 24 | Sep 24 09:11:14 PM UTC 24 | 45342859 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2835868822 | Sep 24 09:11:11 PM UTC 24 | Sep 24 09:11:14 PM UTC 24 | 15965830 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1776439175 | Sep 24 09:11:07 PM UTC 24 | Sep 24 09:11:14 PM UTC 24 | 391323813 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2941047129 | Sep 24 09:11:10 PM UTC 24 | Sep 24 09:11:15 PM UTC 24 | 70712710 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.51504006 | Sep 24 09:11:13 PM UTC 24 | Sep 24 09:11:16 PM UTC 24 | 60264863 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2805296624 | Sep 24 09:11:11 PM UTC 24 | Sep 24 09:11:16 PM UTC 24 | 37988612 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1071182428 | Sep 24 09:11:12 PM UTC 24 | Sep 24 09:11:16 PM UTC 24 | 37140118 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.384355937 | Sep 24 09:11:11 PM UTC 24 | Sep 24 09:11:16 PM UTC 24 | 102009015 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3089428052 | Sep 24 09:11:13 PM UTC 24 | Sep 24 09:11:17 PM UTC 24 | 325113298 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1887178875 | Sep 24 09:11:14 PM UTC 24 | Sep 24 09:11:17 PM UTC 24 | 16376316 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2962703409 | Sep 24 09:11:14 PM UTC 24 | Sep 24 09:11:17 PM UTC 24 | 52814581 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3062114427 | Sep 24 09:11:15 PM UTC 24 | Sep 24 09:11:18 PM UTC 24 | 192360356 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3338126414 | Sep 24 09:11:16 PM UTC 24 | Sep 24 09:11:18 PM UTC 24 | 61483632 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1226064464 | Sep 24 09:11:14 PM UTC 24 | Sep 24 09:11:19 PM UTC 24 | 592579495 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.843887866 | Sep 24 09:11:18 PM UTC 24 | Sep 24 09:11:20 PM UTC 24 | 47621289 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4075867739 | Sep 24 09:11:16 PM UTC 24 | Sep 24 09:11:20 PM UTC 24 | 76572549 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.4196330035 | Sep 24 09:11:18 PM UTC 24 | Sep 24 09:11:20 PM UTC 24 | 21131654 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.520597343 | Sep 24 09:11:17 PM UTC 24 | Sep 24 09:11:22 PM UTC 24 | 307660074 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.66984531 | Sep 24 09:11:17 PM UTC 24 | Sep 24 09:11:22 PM UTC 24 | 172483478 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1690116934 | Sep 24 09:11:25 PM UTC 24 | Sep 24 09:11:27 PM UTC 24 | 51989361 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.969982629 | Sep 24 09:11:19 PM UTC 24 | Sep 24 09:11:22 PM UTC 24 | 133330445 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2119018527 | Sep 24 09:11:18 PM UTC 24 | Sep 24 09:11:23 PM UTC 24 | 353582683 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1399111250 | Sep 24 09:11:19 PM UTC 24 | Sep 24 09:11:23 PM UTC 24 | 571227249 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2548513473 | Sep 24 09:11:14 PM UTC 24 | Sep 24 09:11:23 PM UTC 24 | 285854404 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2387629895 | Sep 24 09:11:19 PM UTC 24 | Sep 24 09:11:24 PM UTC 24 | 72597379 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1633945486 | Sep 24 09:11:22 PM UTC 24 | Sep 24 09:11:25 PM UTC 24 | 30089491 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1071452828 | Sep 24 09:11:18 PM UTC 24 | Sep 24 09:11:25 PM UTC 24 | 194704949 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2613283968 | Sep 24 09:11:23 PM UTC 24 | Sep 24 09:11:26 PM UTC 24 | 21338078 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1038215267 | Sep 24 09:11:22 PM UTC 24 | Sep 24 09:11:27 PM UTC 24 | 255749592 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1251486321 | Sep 24 09:11:20 PM UTC 24 | Sep 24 09:11:27 PM UTC 24 | 144862020 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.355823164 | Sep 24 09:11:25 PM UTC 24 | Sep 24 09:11:27 PM UTC 24 | 45973599 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3515245394 | Sep 24 09:11:23 PM UTC 24 | Sep 24 09:11:28 PM UTC 24 | 55848574 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3737013294 | Sep 24 09:11:23 PM UTC 24 | Sep 24 09:11:28 PM UTC 24 | 84657835 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2212264954 | Sep 24 09:11:23 PM UTC 24 | Sep 24 09:11:28 PM UTC 24 | 100401346 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.96056586 | Sep 24 09:11:25 PM UTC 24 | Sep 24 09:11:30 PM UTC 24 | 326561735 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.364436590 | Sep 24 09:11:25 PM UTC 24 | Sep 24 09:11:30 PM UTC 24 | 203743412 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4204389324 | Sep 24 09:11:27 PM UTC 24 | Sep 24 09:11:30 PM UTC 24 | 37724922 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2718544467 | Sep 24 09:11:26 PM UTC 24 | Sep 24 09:11:31 PM UTC 24 | 340129450 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.739701285 | Sep 24 09:11:26 PM UTC 24 | Sep 24 09:11:31 PM UTC 24 | 56540999 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.411490968 | Sep 24 09:11:29 PM UTC 24 | Sep 24 09:11:31 PM UTC 24 | 63705378 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.3965000293 | Sep 24 09:11:29 PM UTC 24 | Sep 24 09:11:31 PM UTC 24 | 24553836 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2838891334 | Sep 24 09:11:29 PM UTC 24 | Sep 24 09:11:32 PM UTC 24 | 42313952 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1239174773 | Sep 24 09:11:29 PM UTC 24 | Sep 24 09:11:32 PM UTC 24 | 25899442 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.685749974 | Sep 24 09:11:29 PM UTC 24 | Sep 24 09:11:33 PM UTC 24 | 194497413 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.3102215311 | Sep 24 09:11:31 PM UTC 24 | Sep 24 09:11:33 PM UTC 24 | 16338939 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.94596926 | Sep 24 09:11:31 PM UTC 24 | Sep 24 09:11:33 PM UTC 24 | 35765137 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2509897799 | Sep 24 09:11:31 PM UTC 24 | Sep 24 09:11:33 PM UTC 24 | 15716887 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.687684841 | Sep 24 09:11:31 PM UTC 24 | Sep 24 09:11:33 PM UTC 24 | 14230502 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.445009862 | Sep 24 09:11:31 PM UTC 24 | Sep 24 09:11:34 PM UTC 24 | 48210749 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.518426076 | Sep 24 09:11:29 PM UTC 24 | Sep 24 09:11:35 PM UTC 24 | 162767037 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3235412154 | Sep 24 09:11:41 PM UTC 24 | Sep 24 09:11:43 PM UTC 24 | 14064392 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.304466001 | Sep 24 09:11:41 PM UTC 24 | Sep 24 09:11:43 PM UTC 24 | 34001625 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.306654141 | Sep 24 09:11:41 PM UTC 24 | Sep 24 09:11:43 PM UTC 24 | 23730672 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1644680137 | Sep 24 09:11:41 PM UTC 24 | Sep 24 09:11:43 PM UTC 24 | 20094547 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.4071099903 | Sep 24 09:11:41 PM UTC 24 | Sep 24 09:11:43 PM UTC 24 | 20940545 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.1815511182 | Sep 24 09:11:41 PM UTC 24 | Sep 24 09:11:43 PM UTC 24 | 28546713 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.3241576246 | Sep 24 09:11:43 PM UTC 24 | Sep 24 09:11:45 PM UTC 24 | 18088583 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.3168899705 | Sep 24 09:11:43 PM UTC 24 | Sep 24 09:11:45 PM UTC 24 | 35563303 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.3439147691 | Sep 24 09:11:43 PM UTC 24 | Sep 24 09:11:45 PM UTC 24 | 50242481 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.2734636678 | Sep 24 09:11:43 PM UTC 24 | Sep 24 09:11:45 PM UTC 24 | 11296883 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1194871109 | Sep 24 09:11:43 PM UTC 24 | Sep 24 09:11:45 PM UTC 24 | 88536823 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.3923540559 | Sep 24 09:11:43 PM UTC 24 | Sep 24 09:11:45 PM UTC 24 | 32186099 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.3044220037 | Sep 24 09:11:43 PM UTC 24 | Sep 24 09:11:45 PM UTC 24 | 13759216 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3523938984 | Sep 24 09:11:43 PM UTC 24 | Sep 24 09:11:46 PM UTC 24 | 28473852 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.3868649131 | Sep 24 09:11:43 PM UTC 24 | Sep 24 09:11:46 PM UTC 24 | 17824526 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.3071065370 | Sep 24 09:11:43 PM UTC 24 | Sep 24 09:11:46 PM UTC 24 | 34597337 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3760750714 | Sep 24 09:11:45 PM UTC 24 | Sep 24 09:11:47 PM UTC 24 | 49731871 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.1936619750 | Sep 24 09:11:45 PM UTC 24 | Sep 24 09:11:47 PM UTC 24 | 13687135 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2568047417 | Sep 24 09:11:45 PM UTC 24 | Sep 24 09:11:47 PM UTC 24 | 11101968 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.3273190916 | Sep 24 09:11:45 PM UTC 24 | Sep 24 09:11:47 PM UTC 24 | 19091582 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.261196224 | Sep 24 09:11:45 PM UTC 24 | Sep 24 09:11:47 PM UTC 24 | 26836230 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3278482578 | Sep 24 09:11:45 PM UTC 24 | Sep 24 09:11:47 PM UTC 24 | 14016732 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2876798313 | Sep 24 09:11:47 PM UTC 24 | Sep 24 09:11:49 PM UTC 24 | 14711309 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.4003236999 | Sep 24 09:11:47 PM UTC 24 | Sep 24 09:11:49 PM UTC 24 | 12034422 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3452135725 | Sep 24 09:11:47 PM UTC 24 | Sep 24 09:11:49 PM UTC 24 | 25683381 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.953617487 | Sep 24 09:11:47 PM UTC 24 | Sep 24 09:11:49 PM UTC 24 | 13878810 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.2283447423 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2431426581 ps |
| CPU time | 23.43 seconds |
| Started | Sep 24 08:00:39 PM UTC 24 |
| Finished | Sep 24 08:01:04 PM UTC 24 |
| Peak memory | 233724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283447423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2283447423 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.690805707 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14084183882 ps |
| CPU time | 39.6 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:01:14 PM UTC 24 |
| Peak memory | 234284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690805707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.690805707 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.2647319963 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 20875319510 ps |
| CPU time | 30.89 seconds |
| Started | Sep 24 08:00:39 PM UTC 24 |
| Finished | Sep 24 08:01:12 PM UTC 24 |
| Peak memory | 266496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647319963 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2647319963 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2909283921 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 882878005 ps |
| CPU time | 4.66 seconds |
| Started | Sep 24 09:09:18 PM UTC 24 |
| Finished | Sep 24 09:09:23 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909283921 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw. 2909283921 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all_with_rand_reset.2561962808 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 30598564348 ps |
| CPU time | 224.72 seconds |
| Started | Sep 24 08:05:02 PM UTC 24 |
| Finished | Sep 24 08:08:50 PM UTC 24 |
| Peak memory | 310436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2561962808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_ with_rand_reset.2561962808 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.3285738226 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1958223667 ps |
| CPU time | 56.53 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:01:34 PM UTC 24 |
| Peak memory | 295724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285738226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3285738226 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.3278892547 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4907920789 ps |
| CPU time | 7.84 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:00:45 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278892547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3278892547 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.3013010522 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 105393095 ps |
| CPU time | 2.22 seconds |
| Started | Sep 24 08:00:39 PM UTC 24 |
| Finished | Sep 24 08:00:43 PM UTC 24 |
| Peak memory | 227356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013010522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3013010522 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.696521609 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 8267299155 ps |
| CPU time | 133.13 seconds |
| Started | Sep 24 08:04:51 PM UTC 24 |
| Finished | Sep 24 08:07:07 PM UTC 24 |
| Peak memory | 279644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696521609 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.696521609 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.2364371447 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 48310974 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 09:09:44 PM UTC 24 |
| Finished | Sep 24 09:09:47 PM UTC 24 |
| Peak memory | 218648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364371447 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2364371447 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.3591299437 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 154495059 ps |
| CPU time | 2.3 seconds |
| Started | Sep 24 08:15:19 PM UTC 24 |
| Finished | Sep 24 08:15:22 PM UTC 24 |
| Peak memory | 227340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591299437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3591299437 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.1658894995 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1053590994 ps |
| CPU time | 33.01 seconds |
| Started | Sep 24 08:07:00 PM UTC 24 |
| Finished | Sep 24 08:07:35 PM UTC 24 |
| Peak memory | 252892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658894995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1658894995 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.199861378 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 208870374 ps |
| CPU time | 4.56 seconds |
| Started | Sep 24 09:09:24 PM UTC 24 |
| Finished | Sep 24 09:09:30 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199861378 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.199861378 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.1704780833 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1445698628 ps |
| CPU time | 27.59 seconds |
| Started | Sep 24 08:17:48 PM UTC 24 |
| Finished | Sep 24 08:18:17 PM UTC 24 |
| Peak memory | 250632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704780833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1704780833 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.3367840970 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 48860165479 ps |
| CPU time | 472.38 seconds |
| Started | Sep 24 08:12:21 PM UTC 24 |
| Finished | Sep 24 08:20:21 PM UTC 24 |
| Peak memory | 578340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367840970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3367840970 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.265997383 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8415804588 ps |
| CPU time | 516.54 seconds |
| Started | Sep 24 08:03:45 PM UTC 24 |
| Finished | Sep 24 08:12:30 PM UTC 24 |
| Peak memory | 242800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265997383 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.265997383 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.1529316787 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 19024936 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 09:09:53 PM UTC 24 |
| Finished | Sep 24 09:09:56 PM UTC 24 |
| Peak memory | 228680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529316787 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.1529316787 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.670574197 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 58753455 ps |
| CPU time | 2.06 seconds |
| Started | Sep 24 08:42:17 PM UTC 24 |
| Finished | Sep 24 08:42:20 PM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670574197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.670574197 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.3736083696 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 7134453977 ps |
| CPU time | 56.27 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:01:33 PM UTC 24 |
| Peak memory | 256692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736083696 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.3736083696 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.1021950475 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 38983657 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 08:00:39 PM UTC 24 |
| Finished | Sep 24 08:00:42 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021950475 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1021950475 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.1296337832 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 10994974629 ps |
| CPU time | 128.67 seconds |
| Started | Sep 24 08:00:40 PM UTC 24 |
| Finished | Sep 24 08:02:52 PM UTC 24 |
| Peak memory | 279600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296337832 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.1296337832 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2937963218 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 56289701 ps |
| CPU time | 2.01 seconds |
| Started | Sep 24 09:10:01 PM UTC 24 |
| Finished | Sep 24 09:10:04 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937963218 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.2937963218 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.1415468131 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 26649582192 ps |
| CPU time | 739.52 seconds |
| Started | Sep 24 08:47:55 PM UTC 24 |
| Finished | Sep 24 09:00:25 PM UTC 24 |
| Peak memory | 248628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415468131 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1415468131 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.384355937 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 102009015 ps |
| CPU time | 3.77 seconds |
| Started | Sep 24 09:11:11 PM UTC 24 |
| Finished | Sep 24 09:11:16 PM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384355937 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.384355937 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.1730134078 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 39675738232 ps |
| CPU time | 525.08 seconds |
| Started | Sep 24 08:12:49 PM UTC 24 |
| Finished | Sep 24 08:21:42 PM UTC 24 |
| Peak memory | 603224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730134078 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1730134078 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2548513473 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 285854404 ps |
| CPU time | 7.68 seconds |
| Started | Sep 24 09:11:14 PM UTC 24 |
| Finished | Sep 24 09:11:23 PM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548513473 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2548513473 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.1033532272 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3722830606 ps |
| CPU time | 178.89 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:03:37 PM UTC 24 |
| Peak memory | 238568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033532272 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1033532 272 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.2145010929 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 11700114063 ps |
| CPU time | 299.13 seconds |
| Started | Sep 24 08:10:14 PM UTC 24 |
| Finished | Sep 24 08:15:18 PM UTC 24 |
| Peak memory | 504828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145010929 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2145010929 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.2622059883 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 357285523 ps |
| CPU time | 4.39 seconds |
| Started | Sep 24 09:09:41 PM UTC 24 |
| Finished | Sep 24 09:09:47 PM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622059883 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.2622059883 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3858169935 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 221414188 ps |
| CPU time | 4.08 seconds |
| Started | Sep 24 09:10:59 PM UTC 24 |
| Finished | Sep 24 09:11:04 PM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858169935 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3858169935 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.364436590 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 203743412 ps |
| CPU time | 3.9 seconds |
| Started | Sep 24 09:11:25 PM UTC 24 |
| Finished | Sep 24 09:11:30 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364436590 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.364436590 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.938673238 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3361613095 ps |
| CPU time | 318.23 seconds |
| Started | Sep 24 08:00:33 PM UTC 24 |
| Finished | Sep 24 08:05:56 PM UTC 24 |
| Peak memory | 340720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938673238 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.938673238 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.2678280686 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 20962477803 ps |
| CPU time | 481.14 seconds |
| Started | Sep 24 08:38:52 PM UTC 24 |
| Finished | Sep 24 08:47:00 PM UTC 24 |
| Peak memory | 392292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678280686 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2678280686 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.3363374882 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14096327947 ps |
| CPU time | 315.53 seconds |
| Started | Sep 24 08:33:50 PM UTC 24 |
| Finished | Sep 24 08:39:10 PM UTC 24 |
| Peak memory | 529244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363374882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3363374882 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.3293153652 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3151799952 ps |
| CPU time | 115.42 seconds |
| Started | Sep 24 08:09:53 PM UTC 24 |
| Finished | Sep 24 08:11:51 PM UTC 24 |
| Peak memory | 254776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3293153652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_ with_rand_reset.3293153652 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.2670308207 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2152767108 ps |
| CPU time | 14.9 seconds |
| Started | Sep 24 09:09:30 PM UTC 24 |
| Finished | Sep 24 09:09:47 PM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670308207 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2670308207 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.2896214887 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 2314425862 ps |
| CPU time | 15.79 seconds |
| Started | Sep 24 09:09:29 PM UTC 24 |
| Finished | Sep 24 09:09:47 PM UTC 24 |
| Peak memory | 219528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896214887 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2896214887 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1717044408 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 18570593 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 09:09:28 PM UTC 24 |
| Finished | Sep 24 09:09:32 PM UTC 24 |
| Peak memory | 218804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717044408 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1717044408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1310091615 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 174292533 ps |
| CPU time | 2.44 seconds |
| Started | Sep 24 09:09:33 PM UTC 24 |
| Finished | Sep 24 09:09:36 PM UTC 24 |
| Peak memory | 236264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1310091615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_ mem_rw_with_rand_reset.1310091615 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.2232125793 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 74047769 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 09:09:28 PM UTC 24 |
| Finished | Sep 24 09:09:32 PM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232125793 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2232125793 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.2585075449 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 32664567 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 09:09:25 PM UTC 24 |
| Finished | Sep 24 09:09:27 PM UTC 24 |
| Peak memory | 218684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585075449 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2585075449 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.1336417665 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 52105061 ps |
| CPU time | 1.93 seconds |
| Started | Sep 24 09:09:21 PM UTC 24 |
| Finished | Sep 24 09:09:24 PM UTC 24 |
| Peak memory | 228616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336417665 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.1336417665 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.1495392342 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 26495326 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 09:09:18 PM UTC 24 |
| Finished | Sep 24 09:09:20 PM UTC 24 |
| Peak memory | 218416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495392342 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1495392342 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.393593769 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 97626395 ps |
| CPU time | 3.46 seconds |
| Started | Sep 24 09:09:33 PM UTC 24 |
| Finished | Sep 24 09:09:37 PM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393593769 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.393593769 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1440797000 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 71299310 ps |
| CPU time | 1.59 seconds |
| Started | Sep 24 09:09:18 PM UTC 24 |
| Finished | Sep 24 09:09:20 PM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440797000 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.1440797000 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.1155522642 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 251208160 ps |
| CPU time | 5.46 seconds |
| Started | Sep 24 09:09:21 PM UTC 24 |
| Finished | Sep 24 09:09:28 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155522642 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1155522642 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.453196393 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 263176817 ps |
| CPU time | 7.28 seconds |
| Started | Sep 24 09:09:48 PM UTC 24 |
| Finished | Sep 24 09:09:56 PM UTC 24 |
| Peak memory | 219124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453196393 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.453196393 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2770304091 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 524703334 ps |
| CPU time | 11.51 seconds |
| Started | Sep 24 09:09:48 PM UTC 24 |
| Finished | Sep 24 09:10:00 PM UTC 24 |
| Peak memory | 219100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770304091 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2770304091 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.3491097057 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 55810769 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 09:09:44 PM UTC 24 |
| Finished | Sep 24 09:09:47 PM UTC 24 |
| Peak memory | 228736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491097057 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3491097057 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1694715518 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 175016768 ps |
| CPU time | 3.81 seconds |
| Started | Sep 24 09:09:49 PM UTC 24 |
| Finished | Sep 24 09:09:54 PM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1694715518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_ mem_rw_with_rand_reset.1694715518 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.536115366 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 82572619 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 09:09:46 PM UTC 24 |
| Finished | Sep 24 09:09:49 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536115366 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.536115366 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.3802096787 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 63412709 ps |
| CPU time | 1.94 seconds |
| Started | Sep 24 09:09:40 PM UTC 24 |
| Finished | Sep 24 09:09:43 PM UTC 24 |
| Peak memory | 228760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802096787 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.3802096787 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.1156832238 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 14638412 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 09:09:38 PM UTC 24 |
| Finished | Sep 24 09:09:40 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156832238 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1156832238 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.795071446 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 146587868 ps |
| CPU time | 2.21 seconds |
| Started | Sep 24 09:09:48 PM UTC 24 |
| Finished | Sep 24 09:09:51 PM UTC 24 |
| Peak memory | 229436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795071446 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.795071446 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1617811103 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 163467712 ps |
| CPU time | 2.04 seconds |
| Started | Sep 24 09:09:36 PM UTC 24 |
| Finished | Sep 24 09:09:39 PM UTC 24 |
| Peak memory | 230064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617811103 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.1617811103 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2831564985 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 107590963 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 09:09:37 PM UTC 24 |
| Finished | Sep 24 09:09:40 PM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831564985 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw. 2831564985 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.404747496 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1284165095 ps |
| CPU time | 3.04 seconds |
| Started | Sep 24 09:09:41 PM UTC 24 |
| Finished | Sep 24 09:09:45 PM UTC 24 |
| Peak memory | 229568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404747496 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.404747496 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1300685808 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 129254666 ps |
| CPU time | 2.73 seconds |
| Started | Sep 24 09:10:57 PM UTC 24 |
| Finished | Sep 24 09:11:02 PM UTC 24 |
| Peak memory | 236588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1300685808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr _mem_rw_with_rand_reset.1300685808 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.2154294121 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 23738896 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 09:10:56 PM UTC 24 |
| Finished | Sep 24 09:10:58 PM UTC 24 |
| Peak memory | 218744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154294121 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2154294121 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3256393329 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 16973596 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 09:10:56 PM UTC 24 |
| Finished | Sep 24 09:10:58 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256393329 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3256393329 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1875264053 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 360633066 ps |
| CPU time | 2.53 seconds |
| Started | Sep 24 09:10:56 PM UTC 24 |
| Finished | Sep 24 09:10:59 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875264053 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.1875264053 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.382249738 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 49927169 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 09:10:52 PM UTC 24 |
| Finished | Sep 24 09:10:54 PM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382249738 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.382249738 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1433343643 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 611724784 ps |
| CPU time | 2.98 seconds |
| Started | Sep 24 09:10:52 PM UTC 24 |
| Finished | Sep 24 09:10:56 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433343643 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw .1433343643 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2737385477 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 445556808 ps |
| CPU time | 4.24 seconds |
| Started | Sep 24 09:10:54 PM UTC 24 |
| Finished | Sep 24 09:11:00 PM UTC 24 |
| Peak memory | 233720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737385477 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2737385477 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.1719480332 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 820112867 ps |
| CPU time | 3.98 seconds |
| Started | Sep 24 09:10:56 PM UTC 24 |
| Finished | Sep 24 09:11:01 PM UTC 24 |
| Peak memory | 229436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719480332 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1719480332 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1241587051 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 23286934 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 09:11:01 PM UTC 24 |
| Finished | Sep 24 09:11:05 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1241587051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr _mem_rw_with_rand_reset.1241587051 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.2085509307 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 27524453 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 09:11:00 PM UTC 24 |
| Finished | Sep 24 09:11:02 PM UTC 24 |
| Peak memory | 218744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085509307 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2085509307 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1086582983 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 16165679 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 09:10:59 PM UTC 24 |
| Finished | Sep 24 09:11:01 PM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086582983 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1086582983 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3061604625 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 36448530 ps |
| CPU time | 2.89 seconds |
| Started | Sep 24 09:11:00 PM UTC 24 |
| Finished | Sep 24 09:11:04 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061604625 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.3061604625 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.120774351 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 33822410 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 09:10:57 PM UTC 24 |
| Finished | Sep 24 09:11:01 PM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120774351 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.120774351 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1203184806 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 78403227 ps |
| CPU time | 3.42 seconds |
| Started | Sep 24 09:10:57 PM UTC 24 |
| Finished | Sep 24 09:11:02 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203184806 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw .1203184806 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3862743165 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 109918902 ps |
| CPU time | 3.64 seconds |
| Started | Sep 24 09:10:57 PM UTC 24 |
| Finished | Sep 24 09:11:03 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862743165 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3862743165 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3382797201 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 66363694 ps |
| CPU time | 2.57 seconds |
| Started | Sep 24 09:11:06 PM UTC 24 |
| Finished | Sep 24 09:11:09 PM UTC 24 |
| Peak memory | 231572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3382797201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr _mem_rw_with_rand_reset.3382797201 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.256144169 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 29726889 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 09:11:03 PM UTC 24 |
| Finished | Sep 24 09:11:06 PM UTC 24 |
| Peak memory | 228748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256144169 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.256144169 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2655018548 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 13852626 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 09:11:03 PM UTC 24 |
| Finished | Sep 24 09:11:06 PM UTC 24 |
| Peak memory | 218592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655018548 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2655018548 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.4163823473 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 51961049 ps |
| CPU time | 2.43 seconds |
| Started | Sep 24 09:11:04 PM UTC 24 |
| Finished | Sep 24 09:11:08 PM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163823473 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.4163823473 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1856888730 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 76956022 ps |
| CPU time | 1.59 seconds |
| Started | Sep 24 09:11:01 PM UTC 24 |
| Finished | Sep 24 09:11:04 PM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856888730 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.1856888730 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.445007772 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 213739597 ps |
| CPU time | 2.85 seconds |
| Started | Sep 24 09:11:02 PM UTC 24 |
| Finished | Sep 24 09:11:06 PM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445007772 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw. 445007772 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.1990995038 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 304692877 ps |
| CPU time | 2.9 seconds |
| Started | Sep 24 09:11:02 PM UTC 24 |
| Finished | Sep 24 09:11:06 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990995038 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1990995038 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.427193657 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 266071440 ps |
| CPU time | 3.76 seconds |
| Started | Sep 24 09:11:03 PM UTC 24 |
| Finished | Sep 24 09:11:08 PM UTC 24 |
| Peak memory | 219472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427193657 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.427193657 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2741390163 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 339999519 ps |
| CPU time | 3.85 seconds |
| Started | Sep 24 09:11:08 PM UTC 24 |
| Finished | Sep 24 09:11:14 PM UTC 24 |
| Peak memory | 231572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2741390163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr _mem_rw_with_rand_reset.2741390163 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.1275445702 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 240846006 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 09:11:07 PM UTC 24 |
| Finished | Sep 24 09:11:10 PM UTC 24 |
| Peak memory | 218744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275445702 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1275445702 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.1938041007 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 44426268 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 09:11:07 PM UTC 24 |
| Finished | Sep 24 09:11:09 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938041007 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1938041007 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3827013231 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 40396274 ps |
| CPU time | 2.21 seconds |
| Started | Sep 24 09:11:07 PM UTC 24 |
| Finished | Sep 24 09:11:11 PM UTC 24 |
| Peak memory | 229716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827013231 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.3827013231 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1818166847 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 111148474 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 09:11:06 PM UTC 24 |
| Finished | Sep 24 09:11:09 PM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818166847 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.1818166847 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.4120396518 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 170164011 ps |
| CPU time | 4.07 seconds |
| Started | Sep 24 09:11:06 PM UTC 24 |
| Finished | Sep 24 09:11:11 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120396518 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.4120396518 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1776439175 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 391323813 ps |
| CPU time | 6 seconds |
| Started | Sep 24 09:11:07 PM UTC 24 |
| Finished | Sep 24 09:11:14 PM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776439175 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1776439175 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1071182428 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 37140118 ps |
| CPU time | 3.41 seconds |
| Started | Sep 24 09:11:12 PM UTC 24 |
| Finished | Sep 24 09:11:16 PM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1071182428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr _mem_rw_with_rand_reset.1071182428 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2835868822 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 15965830 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 09:11:11 PM UTC 24 |
| Finished | Sep 24 09:11:14 PM UTC 24 |
| Peak memory | 218744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835868822 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2835868822 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1062317970 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 45342859 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 09:11:11 PM UTC 24 |
| Finished | Sep 24 09:11:14 PM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062317970 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1062317970 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2805296624 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 37988612 ps |
| CPU time | 3.1 seconds |
| Started | Sep 24 09:11:11 PM UTC 24 |
| Finished | Sep 24 09:11:16 PM UTC 24 |
| Peak memory | 229696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805296624 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.2805296624 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.861189579 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 26123166 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 09:11:10 PM UTC 24 |
| Finished | Sep 24 09:11:12 PM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861189579 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.861189579 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2941047129 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 70712710 ps |
| CPU time | 3.86 seconds |
| Started | Sep 24 09:11:10 PM UTC 24 |
| Finished | Sep 24 09:11:15 PM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941047129 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw .2941047129 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.864654065 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 91251661 ps |
| CPU time | 2.44 seconds |
| Started | Sep 24 09:11:10 PM UTC 24 |
| Finished | Sep 24 09:11:13 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864654065 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.864654065 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4075867739 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 76572549 ps |
| CPU time | 3.44 seconds |
| Started | Sep 24 09:11:16 PM UTC 24 |
| Finished | Sep 24 09:11:20 PM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4075867739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr _mem_rw_with_rand_reset.4075867739 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2962703409 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 52814581 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 09:11:14 PM UTC 24 |
| Finished | Sep 24 09:11:17 PM UTC 24 |
| Peak memory | 228680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962703409 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2962703409 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1887178875 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 16376316 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 09:11:14 PM UTC 24 |
| Finished | Sep 24 09:11:17 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887178875 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1887178875 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3062114427 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 192360356 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 09:11:15 PM UTC 24 |
| Finished | Sep 24 09:11:18 PM UTC 24 |
| Peak memory | 228792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062114427 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.3062114427 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.51504006 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 60264863 ps |
| CPU time | 1.76 seconds |
| Started | Sep 24 09:11:13 PM UTC 24 |
| Finished | Sep 24 09:11:16 PM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51504006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.51504006 +enable_masking= 0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3089428052 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 325113298 ps |
| CPU time | 2.68 seconds |
| Started | Sep 24 09:11:13 PM UTC 24 |
| Finished | Sep 24 09:11:17 PM UTC 24 |
| Peak memory | 236728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089428052 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw .3089428052 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1226064464 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 592579495 ps |
| CPU time | 3.14 seconds |
| Started | Sep 24 09:11:14 PM UTC 24 |
| Finished | Sep 24 09:11:19 PM UTC 24 |
| Peak memory | 229580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226064464 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1226064464 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2387629895 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 72597379 ps |
| CPU time | 3.6 seconds |
| Started | Sep 24 09:11:19 PM UTC 24 |
| Finished | Sep 24 09:11:24 PM UTC 24 |
| Peak memory | 236588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2387629895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr _mem_rw_with_rand_reset.2387629895 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.4196330035 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 21131654 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 09:11:18 PM UTC 24 |
| Finished | Sep 24 09:11:20 PM UTC 24 |
| Peak memory | 218744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196330035 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.4196330035 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.843887866 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 47621289 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 09:11:18 PM UTC 24 |
| Finished | Sep 24 09:11:20 PM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843887866 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.843887866 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2119018527 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 353582683 ps |
| CPU time | 3.45 seconds |
| Started | Sep 24 09:11:18 PM UTC 24 |
| Finished | Sep 24 09:11:23 PM UTC 24 |
| Peak memory | 229696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119018527 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.2119018527 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3338126414 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 61483632 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 09:11:16 PM UTC 24 |
| Finished | Sep 24 09:11:18 PM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338126414 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.3338126414 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.66984531 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 172483478 ps |
| CPU time | 3.23 seconds |
| Started | Sep 24 09:11:17 PM UTC 24 |
| Finished | Sep 24 09:11:22 PM UTC 24 |
| Peak memory | 230204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66984531 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.6 6984531 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.520597343 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 307660074 ps |
| CPU time | 3.06 seconds |
| Started | Sep 24 09:11:17 PM UTC 24 |
| Finished | Sep 24 09:11:22 PM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520597343 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.520597343 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1071452828 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 194704949 ps |
| CPU time | 5.7 seconds |
| Started | Sep 24 09:11:18 PM UTC 24 |
| Finished | Sep 24 09:11:25 PM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071452828 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1071452828 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3515245394 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 55848574 ps |
| CPU time | 3.2 seconds |
| Started | Sep 24 09:11:23 PM UTC 24 |
| Finished | Sep 24 09:11:28 PM UTC 24 |
| Peak memory | 231572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3515245394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr _mem_rw_with_rand_reset.3515245394 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1633945486 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 30089491 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 09:11:22 PM UTC 24 |
| Finished | Sep 24 09:11:25 PM UTC 24 |
| Peak memory | 228740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633945486 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1633945486 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2241714816 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 52475892 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 09:11:22 PM UTC 24 |
| Finished | Sep 24 09:11:24 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241714816 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2241714816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2212264954 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 100401346 ps |
| CPU time | 3.83 seconds |
| Started | Sep 24 09:11:23 PM UTC 24 |
| Finished | Sep 24 09:11:28 PM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212264954 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.2212264954 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.969982629 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 133330445 ps |
| CPU time | 1.87 seconds |
| Started | Sep 24 09:11:19 PM UTC 24 |
| Finished | Sep 24 09:11:22 PM UTC 24 |
| Peak memory | 228556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969982629 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.969982629 +enable_maskin g=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1399111250 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 571227249 ps |
| CPU time | 2.7 seconds |
| Started | Sep 24 09:11:19 PM UTC 24 |
| Finished | Sep 24 09:11:23 PM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399111250 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw .1399111250 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1251486321 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 144862020 ps |
| CPU time | 5.64 seconds |
| Started | Sep 24 09:11:20 PM UTC 24 |
| Finished | Sep 24 09:11:27 PM UTC 24 |
| Peak memory | 229660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251486321 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1251486321 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1038215267 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 255749592 ps |
| CPU time | 4.13 seconds |
| Started | Sep 24 09:11:22 PM UTC 24 |
| Finished | Sep 24 09:11:27 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038215267 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1038215267 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.739701285 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 56540999 ps |
| CPU time | 3.65 seconds |
| Started | Sep 24 09:11:26 PM UTC 24 |
| Finished | Sep 24 09:11:31 PM UTC 24 |
| Peak memory | 236560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=739701285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_ mem_rw_with_rand_reset.739701285 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.355823164 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 45973599 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 09:11:25 PM UTC 24 |
| Finished | Sep 24 09:11:27 PM UTC 24 |
| Peak memory | 218692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355823164 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.355823164 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1690116934 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 51989361 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 09:11:25 PM UTC 24 |
| Finished | Sep 24 09:11:27 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690116934 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1690116934 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2718544467 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 340129450 ps |
| CPU time | 3.57 seconds |
| Started | Sep 24 09:11:26 PM UTC 24 |
| Finished | Sep 24 09:11:31 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718544467 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.2718544467 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2613283968 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 21338078 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 09:11:23 PM UTC 24 |
| Finished | Sep 24 09:11:26 PM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613283968 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.2613283968 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3737013294 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 84657835 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 09:11:23 PM UTC 24 |
| Finished | Sep 24 09:11:28 PM UTC 24 |
| Peak memory | 236932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737013294 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw .3737013294 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.96056586 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 326561735 ps |
| CPU time | 3.73 seconds |
| Started | Sep 24 09:11:25 PM UTC 24 |
| Finished | Sep 24 09:11:30 PM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96056586 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.96056586 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.445009862 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 48210749 ps |
| CPU time | 2.4 seconds |
| Started | Sep 24 09:11:31 PM UTC 24 |
| Finished | Sep 24 09:11:34 PM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=445009862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_ mem_rw_with_rand_reset.445009862 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.3965000293 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 24553836 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 09:11:29 PM UTC 24 |
| Finished | Sep 24 09:11:31 PM UTC 24 |
| Peak memory | 218744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965000293 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3965000293 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.411490968 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 63705378 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 09:11:29 PM UTC 24 |
| Finished | Sep 24 09:11:31 PM UTC 24 |
| Peak memory | 218688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411490968 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.411490968 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1239174773 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 25899442 ps |
| CPU time | 2.18 seconds |
| Started | Sep 24 09:11:29 PM UTC 24 |
| Finished | Sep 24 09:11:32 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239174773 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.1239174773 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4204389324 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 37724922 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 09:11:27 PM UTC 24 |
| Finished | Sep 24 09:11:30 PM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204389324 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.4204389324 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2838891334 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 42313952 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 09:11:29 PM UTC 24 |
| Finished | Sep 24 09:11:32 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838891334 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw .2838891334 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.518426076 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 162767037 ps |
| CPU time | 5.1 seconds |
| Started | Sep 24 09:11:29 PM UTC 24 |
| Finished | Sep 24 09:11:35 PM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518426076 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.518426076 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.685749974 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 194497413 ps |
| CPU time | 2.75 seconds |
| Started | Sep 24 09:11:29 PM UTC 24 |
| Finished | Sep 24 09:11:33 PM UTC 24 |
| Peak memory | 229476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685749974 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.685749974 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.1844505829 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 133717529 ps |
| CPU time | 8.55 seconds |
| Started | Sep 24 09:10:00 PM UTC 24 |
| Finished | Sep 24 09:10:09 PM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844505829 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1844505829 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1803412726 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 601095821 ps |
| CPU time | 12.17 seconds |
| Started | Sep 24 09:09:59 PM UTC 24 |
| Finished | Sep 24 09:10:12 PM UTC 24 |
| Peak memory | 219224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803412726 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1803412726 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.4133562366 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 128189821 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 09:09:56 PM UTC 24 |
| Finished | Sep 24 09:09:59 PM UTC 24 |
| Peak memory | 218712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133562366 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.4133562366 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2898746493 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 27833839 ps |
| CPU time | 2.55 seconds |
| Started | Sep 24 09:10:00 PM UTC 24 |
| Finished | Sep 24 09:10:03 PM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2898746493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_ mem_rw_with_rand_reset.2898746493 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.3168040820 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 81344263 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 09:09:58 PM UTC 24 |
| Finished | Sep 24 09:10:00 PM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168040820 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3168040820 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.35670236 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 40371016 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 09:09:55 PM UTC 24 |
| Finished | Sep 24 09:09:57 PM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35670236 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.35670236 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.2889224028 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 34671582 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 09:09:52 PM UTC 24 |
| Finished | Sep 24 09:09:54 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889224028 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2889224028 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2546616944 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 121336111 ps |
| CPU time | 3.8 seconds |
| Started | Sep 24 09:10:00 PM UTC 24 |
| Finished | Sep 24 09:10:05 PM UTC 24 |
| Peak memory | 229476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546616944 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.2546616944 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2925061939 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 410946566 ps |
| CPU time | 2.27 seconds |
| Started | Sep 24 09:09:49 PM UTC 24 |
| Finished | Sep 24 09:09:52 PM UTC 24 |
| Peak memory | 230064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925061939 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.2925061939 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2963042022 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 159601223 ps |
| CPU time | 2.25 seconds |
| Started | Sep 24 09:09:51 PM UTC 24 |
| Finished | Sep 24 09:09:54 PM UTC 24 |
| Peak memory | 230120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963042022 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw. 2963042022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.2576401636 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 186978545 ps |
| CPU time | 2.58 seconds |
| Started | Sep 24 09:09:55 PM UTC 24 |
| Finished | Sep 24 09:09:59 PM UTC 24 |
| Peak memory | 229792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576401636 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2576401636 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2115829251 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 196503072 ps |
| CPU time | 6.2 seconds |
| Started | Sep 24 09:09:55 PM UTC 24 |
| Finished | Sep 24 09:10:03 PM UTC 24 |
| Peak memory | 229392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115829251 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.2115829251 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.3102215311 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 16338939 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 09:11:31 PM UTC 24 |
| Finished | Sep 24 09:11:33 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102215311 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3102215311 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2509897799 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 15716887 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 09:11:31 PM UTC 24 |
| Finished | Sep 24 09:11:33 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509897799 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2509897799 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.94596926 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 35765137 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 09:11:31 PM UTC 24 |
| Finished | Sep 24 09:11:33 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94596926 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.94596926 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.687684841 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 14230502 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 09:11:31 PM UTC 24 |
| Finished | Sep 24 09:11:33 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687684841 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.687684841 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3235412154 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 14064392 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 09:11:41 PM UTC 24 |
| Finished | Sep 24 09:11:43 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235412154 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3235412154 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.304466001 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 34001625 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 09:11:41 PM UTC 24 |
| Finished | Sep 24 09:11:43 PM UTC 24 |
| Peak memory | 218688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304466001 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.304466001 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.306654141 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 23730672 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 09:11:41 PM UTC 24 |
| Finished | Sep 24 09:11:43 PM UTC 24 |
| Peak memory | 218688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306654141 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.306654141 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.1815511182 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 28546713 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 09:11:41 PM UTC 24 |
| Finished | Sep 24 09:11:43 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815511182 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1815511182 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.4071099903 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 20940545 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 09:11:41 PM UTC 24 |
| Finished | Sep 24 09:11:43 PM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071099903 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.4071099903 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1644680137 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 20094547 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 09:11:41 PM UTC 24 |
| Finished | Sep 24 09:11:43 PM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644680137 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1644680137 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.426981681 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 139740012 ps |
| CPU time | 10.47 seconds |
| Started | Sep 24 09:10:10 PM UTC 24 |
| Finished | Sep 24 09:10:22 PM UTC 24 |
| Peak memory | 219152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426981681 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.426981681 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.1330198476 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 1498723241 ps |
| CPU time | 29.92 seconds |
| Started | Sep 24 09:10:10 PM UTC 24 |
| Finished | Sep 24 09:10:41 PM UTC 24 |
| Peak memory | 219148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330198476 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1330198476 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.3416225749 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 142712358 ps |
| CPU time | 1.76 seconds |
| Started | Sep 24 09:10:07 PM UTC 24 |
| Finished | Sep 24 09:10:09 PM UTC 24 |
| Peak memory | 218756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416225749 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3416225749 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.412753995 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 83596778 ps |
| CPU time | 3.88 seconds |
| Started | Sep 24 09:10:11 PM UTC 24 |
| Finished | Sep 24 09:10:16 PM UTC 24 |
| Peak memory | 236580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=412753995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_m em_rw_with_rand_reset.412753995 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.1208753791 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 19367298 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 09:10:08 PM UTC 24 |
| Finished | Sep 24 09:10:10 PM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208753791 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1208753791 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.519462047 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 41744731 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 09:10:07 PM UTC 24 |
| Finished | Sep 24 09:10:09 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519462047 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.519462047 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.244505958 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 58811070 ps |
| CPU time | 2 seconds |
| Started | Sep 24 09:10:04 PM UTC 24 |
| Finished | Sep 24 09:10:07 PM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244505958 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.244505958 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.1823251834 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 27458022 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 09:10:03 PM UTC 24 |
| Finished | Sep 24 09:10:05 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823251834 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1823251834 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2658461697 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 54126293 ps |
| CPU time | 2.49 seconds |
| Started | Sep 24 09:10:10 PM UTC 24 |
| Finished | Sep 24 09:10:14 PM UTC 24 |
| Peak memory | 229468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658461697 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.2658461697 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1095847756 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 110980638 ps |
| CPU time | 3.45 seconds |
| Started | Sep 24 09:10:01 PM UTC 24 |
| Finished | Sep 24 09:10:05 PM UTC 24 |
| Peak memory | 230056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095847756 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw. 1095847756 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.2485865591 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 146479459 ps |
| CPU time | 5.23 seconds |
| Started | Sep 24 09:10:05 PM UTC 24 |
| Finished | Sep 24 09:10:12 PM UTC 24 |
| Peak memory | 234016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485865591 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2485865591 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1311197485 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 373867401 ps |
| CPU time | 6.52 seconds |
| Started | Sep 24 09:10:05 PM UTC 24 |
| Finished | Sep 24 09:10:13 PM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311197485 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.1311197485 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.3439147691 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 50242481 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 09:11:43 PM UTC 24 |
| Finished | Sep 24 09:11:45 PM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439147691 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3439147691 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.3241576246 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 18088583 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 09:11:43 PM UTC 24 |
| Finished | Sep 24 09:11:45 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241576246 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3241576246 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.3168899705 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 35563303 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 09:11:43 PM UTC 24 |
| Finished | Sep 24 09:11:45 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168899705 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.3168899705 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.2734636678 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 11296883 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 09:11:43 PM UTC 24 |
| Finished | Sep 24 09:11:45 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734636678 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2734636678 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.3923540559 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 32186099 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 09:11:43 PM UTC 24 |
| Finished | Sep 24 09:11:45 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923540559 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3923540559 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1194871109 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 88536823 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 09:11:43 PM UTC 24 |
| Finished | Sep 24 09:11:45 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194871109 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1194871109 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.3044220037 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 13759216 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 09:11:43 PM UTC 24 |
| Finished | Sep 24 09:11:45 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044220037 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3044220037 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3523938984 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 28473852 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 09:11:43 PM UTC 24 |
| Finished | Sep 24 09:11:46 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523938984 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3523938984 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.3868649131 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 17824526 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 09:11:43 PM UTC 24 |
| Finished | Sep 24 09:11:46 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868649131 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3868649131 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.3071065370 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 34597337 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 09:11:43 PM UTC 24 |
| Finished | Sep 24 09:11:46 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071065370 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3071065370 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.2506668152 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 484793477 ps |
| CPU time | 13.85 seconds |
| Started | Sep 24 09:10:22 PM UTC 24 |
| Finished | Sep 24 09:10:38 PM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506668152 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2506668152 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3422108046 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1255531146 ps |
| CPU time | 28.32 seconds |
| Started | Sep 24 09:10:20 PM UTC 24 |
| Finished | Sep 24 09:10:50 PM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422108046 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3422108046 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.1949344939 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 29411244 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 09:10:19 PM UTC 24 |
| Finished | Sep 24 09:10:22 PM UTC 24 |
| Peak memory | 228736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949344939 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1949344939 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.209179460 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 153999272 ps |
| CPU time | 3.97 seconds |
| Started | Sep 24 09:10:23 PM UTC 24 |
| Finished | Sep 24 09:10:28 PM UTC 24 |
| Peak memory | 231820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=209179460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_m em_rw_with_rand_reset.209179460 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.4272032528 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 28326408 ps |
| CPU time | 1.79 seconds |
| Started | Sep 24 09:10:19 PM UTC 24 |
| Finished | Sep 24 09:10:22 PM UTC 24 |
| Peak memory | 218716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272032528 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.4272032528 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.414458431 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 38659071 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 09:10:17 PM UTC 24 |
| Finished | Sep 24 09:10:19 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414458431 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.414458431 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.3242997967 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 501093056 ps |
| CPU time | 2.53 seconds |
| Started | Sep 24 09:10:15 PM UTC 24 |
| Finished | Sep 24 09:10:18 PM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242997967 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.3242997967 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.416400905 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 18214137 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 09:10:13 PM UTC 24 |
| Finished | Sep 24 09:10:16 PM UTC 24 |
| Peak memory | 218804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416400905 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.416400905 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.9186009 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 223459872 ps |
| CPU time | 2.2 seconds |
| Started | Sep 24 09:10:23 PM UTC 24 |
| Finished | Sep 24 09:10:26 PM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9186009 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.9186009 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.779021497 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 36558336 ps |
| CPU time | 1.55 seconds |
| Started | Sep 24 09:10:12 PM UTC 24 |
| Finished | Sep 24 09:10:15 PM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779021497 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.779021497 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.322093623 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 96777217 ps |
| CPU time | 3.95 seconds |
| Started | Sep 24 09:10:13 PM UTC 24 |
| Finished | Sep 24 09:10:18 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322093623 -asse rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.3 22093623 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.3757559142 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 486678400 ps |
| CPU time | 5.76 seconds |
| Started | Sep 24 09:10:16 PM UTC 24 |
| Finished | Sep 24 09:10:23 PM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757559142 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3757559142 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.2918575377 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 224786299 ps |
| CPU time | 4.55 seconds |
| Started | Sep 24 09:10:17 PM UTC 24 |
| Finished | Sep 24 09:10:22 PM UTC 24 |
| Peak memory | 229428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918575377 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.2918575377 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3760750714 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 49731871 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 09:11:45 PM UTC 24 |
| Finished | Sep 24 09:11:47 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760750714 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3760750714 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.1936619750 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 13687135 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 09:11:45 PM UTC 24 |
| Finished | Sep 24 09:11:47 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936619750 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1936619750 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2568047417 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 11101968 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 09:11:45 PM UTC 24 |
| Finished | Sep 24 09:11:47 PM UTC 24 |
| Peak memory | 218452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568047417 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2568047417 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.261196224 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 26836230 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 09:11:45 PM UTC 24 |
| Finished | Sep 24 09:11:47 PM UTC 24 |
| Peak memory | 218688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261196224 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.261196224 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3278482578 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 14016732 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 09:11:45 PM UTC 24 |
| Finished | Sep 24 09:11:47 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278482578 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3278482578 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.3273190916 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 19091582 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 09:11:45 PM UTC 24 |
| Finished | Sep 24 09:11:47 PM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273190916 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3273190916 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2876798313 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 14711309 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 09:11:47 PM UTC 24 |
| Finished | Sep 24 09:11:49 PM UTC 24 |
| Peak memory | 218608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876798313 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2876798313 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.4003236999 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 12034422 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 09:11:47 PM UTC 24 |
| Finished | Sep 24 09:11:49 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003236999 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.4003236999 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3452135725 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 25683381 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 09:11:47 PM UTC 24 |
| Finished | Sep 24 09:11:49 PM UTC 24 |
| Peak memory | 218748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452135725 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3452135725 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.953617487 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 13878810 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 09:11:47 PM UTC 24 |
| Finished | Sep 24 09:11:49 PM UTC 24 |
| Peak memory | 218688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953617487 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.953617487 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2663665996 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 78573431 ps |
| CPU time | 4.34 seconds |
| Started | Sep 24 09:10:32 PM UTC 24 |
| Finished | Sep 24 09:10:37 PM UTC 24 |
| Peak memory | 229568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2663665996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_ mem_rw_with_rand_reset.2663665996 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.3229269149 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 106765132 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 09:10:28 PM UTC 24 |
| Finished | Sep 24 09:10:31 PM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229269149 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3229269149 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.3649558399 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 49897833 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 09:10:28 PM UTC 24 |
| Finished | Sep 24 09:10:31 PM UTC 24 |
| Peak memory | 218684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649558399 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3649558399 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.175774537 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 43326999 ps |
| CPU time | 3.4 seconds |
| Started | Sep 24 09:10:30 PM UTC 24 |
| Finished | Sep 24 09:10:35 PM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175774537 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.175774537 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.739004701 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 98441556 ps |
| CPU time | 2.31 seconds |
| Started | Sep 24 09:10:24 PM UTC 24 |
| Finished | Sep 24 09:10:27 PM UTC 24 |
| Peak memory | 230060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739004701 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.739004701 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2906647013 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 103627699 ps |
| CPU time | 4.19 seconds |
| Started | Sep 24 09:10:24 PM UTC 24 |
| Finished | Sep 24 09:10:29 PM UTC 24 |
| Peak memory | 236896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906647013 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw. 2906647013 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.1984071047 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 93843016 ps |
| CPU time | 3.81 seconds |
| Started | Sep 24 09:10:26 PM UTC 24 |
| Finished | Sep 24 09:10:31 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984071047 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1984071047 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1440519728 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 430296007 ps |
| CPU time | 7.49 seconds |
| Started | Sep 24 09:10:27 PM UTC 24 |
| Finished | Sep 24 09:10:36 PM UTC 24 |
| Peak memory | 229700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440519728 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1440519728 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1442479496 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 125992901 ps |
| CPU time | 2.96 seconds |
| Started | Sep 24 09:10:38 PM UTC 24 |
| Finished | Sep 24 09:10:42 PM UTC 24 |
| Peak memory | 231572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1442479496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_ mem_rw_with_rand_reset.1442479496 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.3128071332 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 44374754 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 09:10:37 PM UTC 24 |
| Finished | Sep 24 09:10:40 PM UTC 24 |
| Peak memory | 228684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128071332 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3128071332 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.2434419264 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 19092130 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 09:10:36 PM UTC 24 |
| Finished | Sep 24 09:10:38 PM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434419264 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2434419264 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1858449367 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 27185932 ps |
| CPU time | 2.18 seconds |
| Started | Sep 24 09:10:38 PM UTC 24 |
| Finished | Sep 24 09:10:42 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858449367 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.1858449367 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3270425646 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 67252168 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 09:10:32 PM UTC 24 |
| Finished | Sep 24 09:10:35 PM UTC 24 |
| Peak memory | 228608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270425646 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.3270425646 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3838046383 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 28405476 ps |
| CPU time | 2.45 seconds |
| Started | Sep 24 09:10:32 PM UTC 24 |
| Finished | Sep 24 09:10:35 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838046383 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw. 3838046383 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.1022898942 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 289782940 ps |
| CPU time | 3.79 seconds |
| Started | Sep 24 09:10:36 PM UTC 24 |
| Finished | Sep 24 09:10:41 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022898942 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1022898942 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.2075700343 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 124979848 ps |
| CPU time | 4.48 seconds |
| Started | Sep 24 09:10:36 PM UTC 24 |
| Finished | Sep 24 09:10:42 PM UTC 24 |
| Peak memory | 229764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075700343 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.2075700343 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3937475460 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 165465312 ps |
| CPU time | 2.93 seconds |
| Started | Sep 24 09:10:43 PM UTC 24 |
| Finished | Sep 24 09:10:47 PM UTC 24 |
| Peak memory | 229604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3937475460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_ mem_rw_with_rand_reset.3937475460 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3430972000 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 19187428 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 09:10:43 PM UTC 24 |
| Finished | Sep 24 09:10:46 PM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430972000 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3430972000 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.804301096 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 53030151 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 09:10:43 PM UTC 24 |
| Finished | Sep 24 09:10:45 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804301096 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.804301096 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3845606354 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 449001743 ps |
| CPU time | 2.63 seconds |
| Started | Sep 24 09:10:43 PM UTC 24 |
| Finished | Sep 24 09:10:47 PM UTC 24 |
| Peak memory | 229788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845606354 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3845606354 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2941456096 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 28666644 ps |
| CPU time | 1.75 seconds |
| Started | Sep 24 09:10:39 PM UTC 24 |
| Finished | Sep 24 09:10:42 PM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941456096 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.2941456096 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3412357584 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 537403817 ps |
| CPU time | 3.95 seconds |
| Started | Sep 24 09:10:41 PM UTC 24 |
| Finished | Sep 24 09:10:46 PM UTC 24 |
| Peak memory | 236488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412357584 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw. 3412357584 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3159949513 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 112042243 ps |
| CPU time | 3.8 seconds |
| Started | Sep 24 09:10:42 PM UTC 24 |
| Finished | Sep 24 09:10:47 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159949513 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3159949513 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1998754337 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 230250575 ps |
| CPU time | 6.9 seconds |
| Started | Sep 24 09:10:43 PM UTC 24 |
| Finished | Sep 24 09:10:51 PM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998754337 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.1998754337 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2215764038 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 76835473 ps |
| CPU time | 2.1 seconds |
| Started | Sep 24 09:10:48 PM UTC 24 |
| Finished | Sep 24 09:10:51 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2215764038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_ mem_rw_with_rand_reset.2215764038 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3154034782 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 25040529 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 09:10:48 PM UTC 24 |
| Finished | Sep 24 09:10:51 PM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154034782 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3154034782 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.4224029194 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 22814797 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 09:10:47 PM UTC 24 |
| Finished | Sep 24 09:10:49 PM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224029194 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.4224029194 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1443681176 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 111729705 ps |
| CPU time | 4.1 seconds |
| Started | Sep 24 09:10:48 PM UTC 24 |
| Finished | Sep 24 09:10:53 PM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443681176 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.1443681176 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.793911958 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 34563053 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 09:10:45 PM UTC 24 |
| Finished | Sep 24 09:10:48 PM UTC 24 |
| Peak memory | 218444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793911958 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.793911958 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1783145095 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 57608000 ps |
| CPU time | 2.53 seconds |
| Started | Sep 24 09:10:47 PM UTC 24 |
| Finished | Sep 24 09:10:50 PM UTC 24 |
| Peak memory | 236860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783145095 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw. 1783145095 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2582886075 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 170527643 ps |
| CPU time | 2.91 seconds |
| Started | Sep 24 09:10:47 PM UTC 24 |
| Finished | Sep 24 09:10:51 PM UTC 24 |
| Peak memory | 229568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582886075 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2582886075 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.3459180630 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 125986673 ps |
| CPU time | 3.38 seconds |
| Started | Sep 24 09:10:47 PM UTC 24 |
| Finished | Sep 24 09:10:51 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459180630 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.3459180630 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2905491489 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 378058343 ps |
| CPU time | 2.9 seconds |
| Started | Sep 24 09:10:52 PM UTC 24 |
| Finished | Sep 24 09:10:56 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2905491489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_ mem_rw_with_rand_reset.2905491489 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3472513902 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 29070948 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 09:10:52 PM UTC 24 |
| Finished | Sep 24 09:10:54 PM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472513902 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3472513902 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.4226331045 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 38528935 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 09:10:52 PM UTC 24 |
| Finished | Sep 24 09:10:54 PM UTC 24 |
| Peak memory | 218744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226331045 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.4226331045 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2775882980 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 287388525 ps |
| CPU time | 3.11 seconds |
| Started | Sep 24 09:10:52 PM UTC 24 |
| Finished | Sep 24 09:10:56 PM UTC 24 |
| Peak memory | 229532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775882980 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.2775882980 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1011576083 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 37778791 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 09:10:48 PM UTC 24 |
| Finished | Sep 24 09:10:51 PM UTC 24 |
| Peak memory | 228556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011576083 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.1011576083 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3681182559 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 102412164 ps |
| CPU time | 3.61 seconds |
| Started | Sep 24 09:10:50 PM UTC 24 |
| Finished | Sep 24 09:10:55 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681182559 -ass ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw. 3681182559 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.1310179764 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 217495123 ps |
| CPU time | 4.7 seconds |
| Started | Sep 24 09:10:52 PM UTC 24 |
| Finished | Sep 24 09:10:58 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310179764 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1310179764 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1697984559 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 140367394 ps |
| CPU time | 3.18 seconds |
| Started | Sep 24 09:10:52 PM UTC 24 |
| Finished | Sep 24 09:10:56 PM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697984559 -assert nopostproc +UV M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.1697984559 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.4096181332 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 17942056077 ps |
| CPU time | 412.92 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:07:35 PM UTC 24 |
| Peak memory | 564272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096181332 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.4096181332 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.2968382894 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 45513715383 ps |
| CPU time | 259.87 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:04:59 PM UTC 24 |
| Peak memory | 387888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968382894 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2968382894 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.1357505931 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 31645612156 ps |
| CPU time | 788.89 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:13:54 PM UTC 24 |
| Peak memory | 250936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357505931 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1357505931 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.2559585004 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2453622828 ps |
| CPU time | 15.72 seconds |
| Started | Sep 24 08:00:38 PM UTC 24 |
| Finished | Sep 24 08:00:55 PM UTC 24 |
| Peak memory | 233548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559585004 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2559585004 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.1577223725 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 116431238 ps |
| CPU time | 4.03 seconds |
| Started | Sep 24 08:00:39 PM UTC 24 |
| Finished | Sep 24 08:00:45 PM UTC 24 |
| Peak memory | 229248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577223725 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1577223725 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.3118383874 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30898088135 ps |
| CPU time | 282.38 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:05:23 PM UTC 24 |
| Peak memory | 429112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118383874 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.3118383874 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.2426841243 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 188197086762 ps |
| CPU time | 782.44 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:13:45 PM UTC 24 |
| Peak memory | 1039156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426841243 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.2426841243 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.2871808516 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 637023953 ps |
| CPU time | 42.45 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:01:20 PM UTC 24 |
| Peak memory | 238584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871808516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2871808516 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.4014130847 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 131186926381 ps |
| CPU time | 1823.79 seconds |
| Started | Sep 24 08:00:39 PM UTC 24 |
| Finished | Sep 24 08:31:25 PM UTC 24 |
| Peak memory | 1624876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014130847 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.4014130847 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.2428584813 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 29784518 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:00:39 PM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428584813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.2428584813 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.286426941 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 56359270 ps |
| CPU time | 2.31 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:00:39 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286426941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve ctors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.286426941 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.2511443552 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 6728451719 ps |
| CPU time | 54.71 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:01:31 PM UTC 24 |
| Peak memory | 252916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511443552 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2511443552 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.3451610897 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 223988171443 ps |
| CPU time | 1970.22 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:33:49 PM UTC 24 |
| Peak memory | 2370204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451610897 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3451610897 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.3936559536 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 132428955887 ps |
| CPU time | 1306.14 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:22:38 PM UTC 24 |
| Peak memory | 1747600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936559536 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3936559536 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.1219514680 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 71975252698 ps |
| CPU time | 1640.87 seconds |
| Started | Sep 24 08:00:35 PM UTC 24 |
| Finished | Sep 24 08:28:16 PM UTC 24 |
| Peak memory | 1122964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219514680 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1219514 680 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.164717135 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 18223130 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:01:36 PM UTC 24 |
| Finished | Sep 24 08:01:39 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164717135 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.164717135 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.2970508203 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3246864290 ps |
| CPU time | 244.71 seconds |
| Started | Sep 24 08:01:05 PM UTC 24 |
| Finished | Sep 24 08:05:13 PM UTC 24 |
| Peak memory | 322604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970508203 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2970508203 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.4251246751 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 33174714077 ps |
| CPU time | 355.45 seconds |
| Started | Sep 24 08:01:07 PM UTC 24 |
| Finished | Sep 24 08:07:07 PM UTC 24 |
| Peak memory | 514868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251246751 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.4251246751 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.2479546166 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 37961534696 ps |
| CPU time | 365.94 seconds |
| Started | Sep 24 08:00:41 PM UTC 24 |
| Finished | Sep 24 08:06:52 PM UTC 24 |
| Peak memory | 250616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479546166 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2479546166 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.2617054734 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2689888261 ps |
| CPU time | 32.82 seconds |
| Started | Sep 24 08:01:30 PM UTC 24 |
| Finished | Sep 24 08:02:04 PM UTC 24 |
| Peak memory | 234024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617054734 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2617054734 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.3608878284 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2603266331 ps |
| CPU time | 28.13 seconds |
| Started | Sep 24 08:01:30 PM UTC 24 |
| Finished | Sep 24 08:02:00 PM UTC 24 |
| Peak memory | 234000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608878284 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.3608878284 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.926821321 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10564494277 ps |
| CPU time | 41.19 seconds |
| Started | Sep 24 08:01:32 PM UTC 24 |
| Finished | Sep 24 08:02:15 PM UTC 24 |
| Peak memory | 234304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926821321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_u nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.926821321 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.205172443 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1525082564 ps |
| CPU time | 23.16 seconds |
| Started | Sep 24 08:01:07 PM UTC 24 |
| Finished | Sep 24 08:01:31 PM UTC 24 |
| Peak memory | 234100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205172443 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.205172443 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.1665092436 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2185355065 ps |
| CPU time | 64.7 seconds |
| Started | Sep 24 08:01:15 PM UTC 24 |
| Finished | Sep 24 08:02:21 PM UTC 24 |
| Peak memory | 266988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665092436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1665092436 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.793413619 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1127064853 ps |
| CPU time | 3.87 seconds |
| Started | Sep 24 08:01:28 PM UTC 24 |
| Finished | Sep 24 08:01:33 PM UTC 24 |
| Peak memory | 227240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793413619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.793413619 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.678046700 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 72117250 ps |
| CPU time | 2.17 seconds |
| Started | Sep 24 08:01:32 PM UTC 24 |
| Finished | Sep 24 08:01:36 PM UTC 24 |
| Peak memory | 227660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678046700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.678046700 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.3493616307 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1352262337 ps |
| CPU time | 103.32 seconds |
| Started | Sep 24 08:01:15 PM UTC 24 |
| Finished | Sep 24 08:03:00 PM UTC 24 |
| Peak memory | 271360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493616307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3493616307 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.391789666 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 20135843955 ps |
| CPU time | 62.93 seconds |
| Started | Sep 24 08:01:36 PM UTC 24 |
| Finished | Sep 24 08:02:41 PM UTC 24 |
| Peak memory | 284808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391789666 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.391789666 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.1921363740 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7168388329 ps |
| CPU time | 231.04 seconds |
| Started | Sep 24 08:00:40 PM UTC 24 |
| Finished | Sep 24 08:04:35 PM UTC 24 |
| Peak memory | 420640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921363740 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1921363740 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.3687296609 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 387986319 ps |
| CPU time | 22.2 seconds |
| Started | Sep 24 08:00:39 PM UTC 24 |
| Finished | Sep 24 08:01:04 PM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687296609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3687296609 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.2652289325 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 58210578772 ps |
| CPU time | 1518.1 seconds |
| Started | Sep 24 08:01:34 PM UTC 24 |
| Finished | Sep 24 08:27:10 PM UTC 24 |
| Peak memory | 1270896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652289325 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2652289325 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.1699463439 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 536671136 ps |
| CPU time | 2.48 seconds |
| Started | Sep 24 08:00:56 PM UTC 24 |
| Finished | Sep 24 08:01:00 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699463439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.1699463439 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.1428749750 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 225033865 ps |
| CPU time | 4.38 seconds |
| Started | Sep 24 08:01:00 PM UTC 24 |
| Finished | Sep 24 08:01:06 PM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428749750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1428749750 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.3961772250 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 334353811443 ps |
| CPU time | 3386.16 seconds |
| Started | Sep 24 08:00:41 PM UTC 24 |
| Finished | Sep 24 08:57:48 PM UTC 24 |
| Peak memory | 3224312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961772250 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3961772250 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.1714689981 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1550588948 ps |
| CPU time | 51.58 seconds |
| Started | Sep 24 08:00:43 PM UTC 24 |
| Finished | Sep 24 08:01:36 PM UTC 24 |
| Peak memory | 234012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714689981 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1714689981 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.2241726165 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 46482453852 ps |
| CPU time | 1836.69 seconds |
| Started | Sep 24 08:00:54 PM UTC 24 |
| Finished | Sep 24 08:31:53 PM UTC 24 |
| Peak memory | 2405020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241726165 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2241726165 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.1298533611 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2044097113 ps |
| CPU time | 29.15 seconds |
| Started | Sep 24 08:00:54 PM UTC 24 |
| Finished | Sep 24 08:01:25 PM UTC 24 |
| Peak memory | 234136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298533611 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1298533611 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.207353926 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 8590212945 ps |
| CPU time | 166.22 seconds |
| Started | Sep 24 08:00:56 PM UTC 24 |
| Finished | Sep 24 08:03:46 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207353926 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.20735392 6 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.4189085604 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 33185109734 ps |
| CPU time | 1792.07 seconds |
| Started | Sep 24 08:00:56 PM UTC 24 |
| Finished | Sep 24 08:31:12 PM UTC 24 |
| Peak memory | 1102680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189085604 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.4189085 604 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.2039815704 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 14942156 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:15:26 PM UTC 24 |
| Finished | Sep 24 08:15:28 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039815704 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2039815704 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.639129486 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2857922976 ps |
| CPU time | 107.53 seconds |
| Started | Sep 24 08:14:41 PM UTC 24 |
| Finished | Sep 24 08:16:31 PM UTC 24 |
| Peak memory | 275248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639129486 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.639129486 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.1735919183 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 2974178105 ps |
| CPU time | 128.8 seconds |
| Started | Sep 24 08:14:38 PM UTC 24 |
| Finished | Sep 24 08:16:50 PM UTC 24 |
| Peak memory | 234228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735919183 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1735919183 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.754043494 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 717559944 ps |
| CPU time | 53.13 seconds |
| Started | Sep 24 08:15:14 PM UTC 24 |
| Finished | Sep 24 08:16:09 PM UTC 24 |
| Peak memory | 233832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754043494 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.754043494 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.3272710100 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2673012502 ps |
| CPU time | 8.95 seconds |
| Started | Sep 24 08:15:15 PM UTC 24 |
| Finished | Sep 24 08:15:25 PM UTC 24 |
| Peak memory | 234308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272710100 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3272710100 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.3818911415 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3075441900 ps |
| CPU time | 101.95 seconds |
| Started | Sep 24 08:14:49 PM UTC 24 |
| Finished | Sep 24 08:16:34 PM UTC 24 |
| Peak memory | 260856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818911415 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3818911415 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.3353318775 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 6513885522 ps |
| CPU time | 136.09 seconds |
| Started | Sep 24 08:15:10 PM UTC 24 |
| Finished | Sep 24 08:17:28 PM UTC 24 |
| Peak memory | 285428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353318775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3353318775 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.3168257120 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 19849092461 ps |
| CPU time | 18.76 seconds |
| Started | Sep 24 08:15:14 PM UTC 24 |
| Finished | Sep 24 08:15:34 PM UTC 24 |
| Peak memory | 227296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168257120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3168257120 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.1759060661 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 25266884310 ps |
| CPU time | 1374.58 seconds |
| Started | Sep 24 08:14:23 PM UTC 24 |
| Finished | Sep 24 08:37:35 PM UTC 24 |
| Peak memory | 1029160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759060661 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.1759060661 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.2191340018 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5060089555 ps |
| CPU time | 40.05 seconds |
| Started | Sep 24 08:14:31 PM UTC 24 |
| Finished | Sep 24 08:15:13 PM UTC 24 |
| Peak memory | 251036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191340018 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2191340018 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.2510802352 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 793005217 ps |
| CPU time | 9.7 seconds |
| Started | Sep 24 08:14:20 PM UTC 24 |
| Finished | Sep 24 08:14:31 PM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510802352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2510802352 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.1136432708 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 153662147383 ps |
| CPU time | 2199.3 seconds |
| Started | Sep 24 08:15:23 PM UTC 24 |
| Finished | Sep 24 08:52:29 PM UTC 24 |
| Peak memory | 1279008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136432708 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1136432708 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.3666184256 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 80600822 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:16:50 PM UTC 24 |
| Finished | Sep 24 08:16:53 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666184256 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3666184256 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.739506119 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 10626889478 ps |
| CPU time | 197.09 seconds |
| Started | Sep 24 08:16:09 PM UTC 24 |
| Finished | Sep 24 08:19:29 PM UTC 24 |
| Peak memory | 384088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739506119 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.739506119 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.2021327466 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 256505770374 ps |
| CPU time | 1370.53 seconds |
| Started | Sep 24 08:15:53 PM UTC 24 |
| Finished | Sep 24 08:39:01 PM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021327466 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2021327466 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.2171664863 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 218209052 ps |
| CPU time | 24.07 seconds |
| Started | Sep 24 08:16:32 PM UTC 24 |
| Finished | Sep 24 08:16:57 PM UTC 24 |
| Peak memory | 234120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171664863 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2171664863 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.1597258864 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1764732805 ps |
| CPU time | 17.03 seconds |
| Started | Sep 24 08:16:34 PM UTC 24 |
| Finished | Sep 24 08:16:53 PM UTC 24 |
| Peak memory | 233508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597258864 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1597258864 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.858503467 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 7597659679 ps |
| CPU time | 153.71 seconds |
| Started | Sep 24 08:16:10 PM UTC 24 |
| Finished | Sep 24 08:18:46 PM UTC 24 |
| Peak memory | 357172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858503467 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.858503467 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.3355565531 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 7580740538 ps |
| CPU time | 127.79 seconds |
| Started | Sep 24 08:16:18 PM UTC 24 |
| Finished | Sep 24 08:18:28 PM UTC 24 |
| Peak memory | 346968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355565531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3355565531 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.2356847154 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 8957229984 ps |
| CPU time | 17.14 seconds |
| Started | Sep 24 08:16:20 PM UTC 24 |
| Finished | Sep 24 08:16:38 PM UTC 24 |
| Peak memory | 227372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356847154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2356847154 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.3531913843 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 47487655 ps |
| CPU time | 2 seconds |
| Started | Sep 24 08:16:39 PM UTC 24 |
| Finished | Sep 24 08:16:42 PM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531913843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3531913843 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.1226012028 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 15649439511 ps |
| CPU time | 341.76 seconds |
| Started | Sep 24 08:15:34 PM UTC 24 |
| Finished | Sep 24 08:21:21 PM UTC 24 |
| Peak memory | 459556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226012028 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.1226012028 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.3216036450 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 19147084776 ps |
| CPU time | 223.37 seconds |
| Started | Sep 24 08:15:38 PM UTC 24 |
| Finished | Sep 24 08:19:26 PM UTC 24 |
| Peak memory | 434940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216036450 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3216036450 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.198268251 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 689795332 ps |
| CPU time | 36.33 seconds |
| Started | Sep 24 08:15:29 PM UTC 24 |
| Finished | Sep 24 08:16:07 PM UTC 24 |
| Peak memory | 233612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198268251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.198268251 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.3674462434 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 280186360254 ps |
| CPU time | 1452.79 seconds |
| Started | Sep 24 08:16:43 PM UTC 24 |
| Finished | Sep 24 08:41:15 PM UTC 24 |
| Peak memory | 642140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674462434 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3674462434 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.2620565903 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 37490528 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:18:07 PM UTC 24 |
| Finished | Sep 24 08:18:09 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620565903 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2620565903 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.411536665 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 19452325214 ps |
| CPU time | 230.31 seconds |
| Started | Sep 24 08:17:10 PM UTC 24 |
| Finished | Sep 24 08:21:04 PM UTC 24 |
| Peak memory | 394352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411536665 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.411536665 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.128565740 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 42071773225 ps |
| CPU time | 303.57 seconds |
| Started | Sep 24 08:16:59 PM UTC 24 |
| Finished | Sep 24 08:22:07 PM UTC 24 |
| Peak memory | 246608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128565740 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.128565740 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.2039832139 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 7888489500 ps |
| CPU time | 49.28 seconds |
| Started | Sep 24 08:17:32 PM UTC 24 |
| Finished | Sep 24 08:18:23 PM UTC 24 |
| Peak memory | 234212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039832139 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2039832139 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.2164933838 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 14139059711 ps |
| CPU time | 56.53 seconds |
| Started | Sep 24 08:17:37 PM UTC 24 |
| Finished | Sep 24 08:18:36 PM UTC 24 |
| Peak memory | 234220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164933838 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2164933838 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.3913295508 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4690809692 ps |
| CPU time | 161.63 seconds |
| Started | Sep 24 08:17:20 PM UTC 24 |
| Finished | Sep 24 08:20:04 PM UTC 24 |
| Peak memory | 298104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913295508 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3913295508 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.1409651670 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 92166831 ps |
| CPU time | 7.48 seconds |
| Started | Sep 24 08:17:23 PM UTC 24 |
| Finished | Sep 24 08:17:32 PM UTC 24 |
| Peak memory | 233648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409651670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1409651670 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.1528759724 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1005421337 ps |
| CPU time | 6.79 seconds |
| Started | Sep 24 08:17:29 PM UTC 24 |
| Finished | Sep 24 08:17:37 PM UTC 24 |
| Peak memory | 227168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528759724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.1528759724 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.3136498397 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 322837787057 ps |
| CPU time | 3193.36 seconds |
| Started | Sep 24 08:16:54 PM UTC 24 |
| Finished | Sep 24 09:10:46 PM UTC 24 |
| Peak memory | 3558184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136498397 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.3136498397 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.303408428 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3850864322 ps |
| CPU time | 104.3 seconds |
| Started | Sep 24 08:16:54 PM UTC 24 |
| Finished | Sep 24 08:18:40 PM UTC 24 |
| Peak memory | 299828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303408428 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.303408428 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.2147652701 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1419986568 ps |
| CPU time | 25.65 seconds |
| Started | Sep 24 08:16:52 PM UTC 24 |
| Finished | Sep 24 08:17:19 PM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147652701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2147652701 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.1771002718 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 257313225619 ps |
| CPU time | 1035.31 seconds |
| Started | Sep 24 08:18:02 PM UTC 24 |
| Finished | Sep 24 08:35:29 PM UTC 24 |
| Peak memory | 1051800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771002718 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1771002718 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.1078810020 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 43299888 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:19:30 PM UTC 24 |
| Finished | Sep 24 08:19:32 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078810020 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.1078810020 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.1034452335 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 9446438201 ps |
| CPU time | 218.87 seconds |
| Started | Sep 24 08:18:36 PM UTC 24 |
| Finished | Sep 24 08:22:19 PM UTC 24 |
| Peak memory | 416604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034452335 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1034452335 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.2845213921 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 30674675221 ps |
| CPU time | 1236.98 seconds |
| Started | Sep 24 08:18:29 PM UTC 24 |
| Finished | Sep 24 08:39:22 PM UTC 24 |
| Peak memory | 265012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845213921 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2845213921 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.2386972099 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3324942206 ps |
| CPU time | 31.88 seconds |
| Started | Sep 24 08:18:52 PM UTC 24 |
| Finished | Sep 24 08:19:26 PM UTC 24 |
| Peak memory | 234280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386972099 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2386972099 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.3382599736 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2001196669 ps |
| CPU time | 19.6 seconds |
| Started | Sep 24 08:19:15 PM UTC 24 |
| Finished | Sep 24 08:19:35 PM UTC 24 |
| Peak memory | 233636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382599736 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3382599736 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.3580260939 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 22282191320 ps |
| CPU time | 308.53 seconds |
| Started | Sep 24 08:18:41 PM UTC 24 |
| Finished | Sep 24 08:23:54 PM UTC 24 |
| Peak memory | 488188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580260939 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3580260939 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.396144358 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 14669261971 ps |
| CPU time | 446.96 seconds |
| Started | Sep 24 08:18:46 PM UTC 24 |
| Finished | Sep 24 08:26:20 PM UTC 24 |
| Peak memory | 621292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396144358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.396144358 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.2981709187 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2256323609 ps |
| CPU time | 16.51 seconds |
| Started | Sep 24 08:19:27 PM UTC 24 |
| Finished | Sep 24 08:19:45 PM UTC 24 |
| Peak memory | 244576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981709187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2981709187 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.1673477025 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 594305458134 ps |
| CPU time | 3920.15 seconds |
| Started | Sep 24 08:18:19 PM UTC 24 |
| Finished | Sep 24 09:24:24 PM UTC 24 |
| Peak memory | 4105104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673477025 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.1673477025 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.1034150218 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 5668967341 ps |
| CPU time | 257.45 seconds |
| Started | Sep 24 08:18:24 PM UTC 24 |
| Finished | Sep 24 08:22:46 PM UTC 24 |
| Peak memory | 320248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034150218 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1034150218 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.4029294697 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5203221553 ps |
| CPU time | 78.77 seconds |
| Started | Sep 24 08:18:10 PM UTC 24 |
| Finished | Sep 24 08:19:31 PM UTC 24 |
| Peak memory | 234328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029294697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.4029294697 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.2425230241 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 112346672457 ps |
| CPU time | 2147.81 seconds |
| Started | Sep 24 08:19:27 PM UTC 24 |
| Finished | Sep 24 08:55:42 PM UTC 24 |
| Peak memory | 818232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425230241 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2425230241 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.944371814 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 47977531 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:21:22 PM UTC 24 |
| Finished | Sep 24 08:21:24 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944371814 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.944371814 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.3072808017 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 6453920736 ps |
| CPU time | 157.85 seconds |
| Started | Sep 24 08:20:05 PM UTC 24 |
| Finished | Sep 24 08:22:46 PM UTC 24 |
| Peak memory | 291612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072808017 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3072808017 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.3803907067 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2821969991 ps |
| CPU time | 294.8 seconds |
| Started | Sep 24 08:19:45 PM UTC 24 |
| Finished | Sep 24 08:24:45 PM UTC 24 |
| Peak memory | 244536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803907067 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3803907067 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.1695684336 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 379977908 ps |
| CPU time | 37.29 seconds |
| Started | Sep 24 08:20:50 PM UTC 24 |
| Finished | Sep 24 08:21:29 PM UTC 24 |
| Peak memory | 234208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695684336 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1695684336 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.2838979524 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 429397783 ps |
| CPU time | 42.38 seconds |
| Started | Sep 24 08:21:04 PM UTC 24 |
| Finished | Sep 24 08:21:48 PM UTC 24 |
| Peak memory | 233832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838979524 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2838979524 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.289594107 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 30190092695 ps |
| CPU time | 208.01 seconds |
| Started | Sep 24 08:20:22 PM UTC 24 |
| Finished | Sep 24 08:23:54 PM UTC 24 |
| Peak memory | 353072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289594107 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.289594107 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.1463095922 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 5632195276 ps |
| CPU time | 95.11 seconds |
| Started | Sep 24 08:20:40 PM UTC 24 |
| Finished | Sep 24 08:22:17 PM UTC 24 |
| Peak memory | 310256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463095922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1463095922 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.477427785 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3475802229 ps |
| CPU time | 6.79 seconds |
| Started | Sep 24 08:20:41 PM UTC 24 |
| Finished | Sep 24 08:20:49 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477427785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.477427785 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.946465053 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 201136588 ps |
| CPU time | 2.21 seconds |
| Started | Sep 24 08:21:05 PM UTC 24 |
| Finished | Sep 24 08:21:09 PM UTC 24 |
| Peak memory | 227364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946465053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.946465053 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.1311034073 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 340538121987 ps |
| CPU time | 3491.65 seconds |
| Started | Sep 24 08:19:33 PM UTC 24 |
| Finished | Sep 24 09:18:25 PM UTC 24 |
| Peak memory | 3570604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311034073 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.1311034073 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.944537562 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 9339528252 ps |
| CPU time | 179.85 seconds |
| Started | Sep 24 08:19:36 PM UTC 24 |
| Finished | Sep 24 08:22:39 PM UTC 24 |
| Peak memory | 310112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944537562 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.944537562 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.2475334408 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1041374582 ps |
| CPU time | 65.31 seconds |
| Started | Sep 24 08:19:32 PM UTC 24 |
| Finished | Sep 24 08:20:39 PM UTC 24 |
| Peak memory | 233644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475334408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2475334408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.2840055913 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 313865602324 ps |
| CPU time | 1184.46 seconds |
| Started | Sep 24 08:21:09 PM UTC 24 |
| Finished | Sep 24 08:41:09 PM UTC 24 |
| Peak memory | 988340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840055913 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2840055913 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.1584865180 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 19645715 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:22:47 PM UTC 24 |
| Finished | Sep 24 08:22:49 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584865180 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1584865180 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.2071266348 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 13698458916 ps |
| CPU time | 100.95 seconds |
| Started | Sep 24 08:22:01 PM UTC 24 |
| Finished | Sep 24 08:23:44 PM UTC 24 |
| Peak memory | 291572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071266348 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2071266348 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.584750615 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4680651520 ps |
| CPU time | 203.34 seconds |
| Started | Sep 24 08:21:49 PM UTC 24 |
| Finished | Sep 24 08:25:16 PM UTC 24 |
| Peak memory | 250864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584750615 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.584750615 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.3353630252 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 24579969495 ps |
| CPU time | 76.89 seconds |
| Started | Sep 24 08:22:38 PM UTC 24 |
| Finished | Sep 24 08:23:57 PM UTC 24 |
| Peak memory | 234028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353630252 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3353630252 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.339380081 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1421739378 ps |
| CPU time | 43.03 seconds |
| Started | Sep 24 08:22:39 PM UTC 24 |
| Finished | Sep 24 08:23:24 PM UTC 24 |
| Peak memory | 234192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339380081 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.339380081 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.2976424032 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 18150403555 ps |
| CPU time | 83.97 seconds |
| Started | Sep 24 08:22:07 PM UTC 24 |
| Finished | Sep 24 08:23:33 PM UTC 24 |
| Peak memory | 279588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976424032 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2976424032 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.971468586 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3664485710 ps |
| CPU time | 185.2 seconds |
| Started | Sep 24 08:22:18 PM UTC 24 |
| Finished | Sep 24 08:25:27 PM UTC 24 |
| Peak memory | 316208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971468586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.971468586 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.1679822334 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1485806299 ps |
| CPU time | 15.88 seconds |
| Started | Sep 24 08:22:19 PM UTC 24 |
| Finished | Sep 24 08:22:36 PM UTC 24 |
| Peak memory | 227360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679822334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1679822334 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.2049792408 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 38281449 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:22:41 PM UTC 24 |
| Finished | Sep 24 08:22:43 PM UTC 24 |
| Peak memory | 226360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049792408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2049792408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.542951052 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 33576490940 ps |
| CPU time | 872 seconds |
| Started | Sep 24 08:21:30 PM UTC 24 |
| Finished | Sep 24 08:36:13 PM UTC 24 |
| Peak memory | 725752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542951052 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.542951052 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.4155541971 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 36606745169 ps |
| CPU time | 458.5 seconds |
| Started | Sep 24 08:21:43 PM UTC 24 |
| Finished | Sep 24 08:29:28 PM UTC 24 |
| Peak memory | 602932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155541971 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.4155541971 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.3878498320 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1266052765 ps |
| CPU time | 33.92 seconds |
| Started | Sep 24 08:21:25 PM UTC 24 |
| Finished | Sep 24 08:22:00 PM UTC 24 |
| Peak memory | 233636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878498320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3878498320 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.2748058989 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10320160290 ps |
| CPU time | 948.16 seconds |
| Started | Sep 24 08:22:44 PM UTC 24 |
| Finished | Sep 24 08:38:45 PM UTC 24 |
| Peak memory | 574296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748058989 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2748058989 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.1683055489 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 27219966 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:23:54 PM UTC 24 |
| Finished | Sep 24 08:23:57 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683055489 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1683055489 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.3730559419 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 17039546389 ps |
| CPU time | 474.05 seconds |
| Started | Sep 24 08:23:18 PM UTC 24 |
| Finished | Sep 24 08:31:20 PM UTC 24 |
| Peak memory | 551988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730559419 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3730559419 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.1433886545 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 20273965806 ps |
| CPU time | 717.6 seconds |
| Started | Sep 24 08:23:11 PM UTC 24 |
| Finished | Sep 24 08:35:19 PM UTC 24 |
| Peak memory | 258808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433886545 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.1433886545 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.3746899905 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 7924976601 ps |
| CPU time | 63.26 seconds |
| Started | Sep 24 08:23:36 PM UTC 24 |
| Finished | Sep 24 08:24:41 PM UTC 24 |
| Peak memory | 234248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746899905 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3746899905 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.4228745316 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1096926965 ps |
| CPU time | 29.25 seconds |
| Started | Sep 24 08:23:45 PM UTC 24 |
| Finished | Sep 24 08:24:16 PM UTC 24 |
| Peak memory | 234092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228745316 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.4228745316 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.2041726338 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1460310288 ps |
| CPU time | 13.28 seconds |
| Started | Sep 24 08:23:21 PM UTC 24 |
| Finished | Sep 24 08:23:35 PM UTC 24 |
| Peak memory | 233680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041726338 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2041726338 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.2621482084 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 13295042877 ps |
| CPU time | 111.4 seconds |
| Started | Sep 24 08:23:25 PM UTC 24 |
| Finished | Sep 24 08:25:18 PM UTC 24 |
| Peak memory | 297752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621482084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2621482084 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.459354379 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3365508942 ps |
| CPU time | 8.85 seconds |
| Started | Sep 24 08:23:35 PM UTC 24 |
| Finished | Sep 24 08:23:45 PM UTC 24 |
| Peak memory | 227400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459354379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.459354379 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.2235332171 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 52241211 ps |
| CPU time | 1.94 seconds |
| Started | Sep 24 08:23:46 PM UTC 24 |
| Finished | Sep 24 08:23:49 PM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235332171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2235332171 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.555121671 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 28598139295 ps |
| CPU time | 2964.78 seconds |
| Started | Sep 24 08:22:50 PM UTC 24 |
| Finished | Sep 24 09:12:49 PM UTC 24 |
| Peak memory | 1905404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555121671 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.555121671 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.3923360338 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 12441858038 ps |
| CPU time | 372.04 seconds |
| Started | Sep 24 08:23:01 PM UTC 24 |
| Finished | Sep 24 08:29:19 PM UTC 24 |
| Peak memory | 490488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923360338 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3923360338 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.4224357127 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 9162729745 ps |
| CPU time | 31.12 seconds |
| Started | Sep 24 08:22:47 PM UTC 24 |
| Finished | Sep 24 08:23:20 PM UTC 24 |
| Peak memory | 233764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224357127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.4224357127 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.3270717201 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 71910264828 ps |
| CPU time | 1104.86 seconds |
| Started | Sep 24 08:23:50 PM UTC 24 |
| Finished | Sep 24 08:42:28 PM UTC 24 |
| Peak memory | 928912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270717201 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.3270717201 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.2182778016 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 13701236 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:25:30 PM UTC 24 |
| Finished | Sep 24 08:25:33 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182778016 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2182778016 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.1583884990 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2810390046 ps |
| CPU time | 68.56 seconds |
| Started | Sep 24 08:24:17 PM UTC 24 |
| Finished | Sep 24 08:25:27 PM UTC 24 |
| Peak memory | 283700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583884990 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1583884990 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.273701225 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 32575668962 ps |
| CPU time | 693.97 seconds |
| Started | Sep 24 08:24:01 PM UTC 24 |
| Finished | Sep 24 08:35:44 PM UTC 24 |
| Peak memory | 250668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273701225 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.273701225 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.1303366867 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 8724282840 ps |
| CPU time | 61.09 seconds |
| Started | Sep 24 08:25:29 PM UTC 24 |
| Finished | Sep 24 08:26:32 PM UTC 24 |
| Peak memory | 244196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303366867 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1303366867 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.1917066999 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1592754114 ps |
| CPU time | 45.02 seconds |
| Started | Sep 24 08:25:29 PM UTC 24 |
| Finished | Sep 24 08:26:16 PM UTC 24 |
| Peak memory | 233868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917066999 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1917066999 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.2524959949 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 26344158690 ps |
| CPU time | 245.91 seconds |
| Started | Sep 24 08:24:42 PM UTC 24 |
| Finished | Sep 24 08:28:52 PM UTC 24 |
| Peak memory | 312376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524959949 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2524959949 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.2995409268 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 24853404524 ps |
| CPU time | 326.85 seconds |
| Started | Sep 24 08:24:46 PM UTC 24 |
| Finished | Sep 24 08:30:18 PM UTC 24 |
| Peak memory | 453428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995409268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2995409268 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.1345428788 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1025286463 ps |
| CPU time | 10.77 seconds |
| Started | Sep 24 08:25:17 PM UTC 24 |
| Finished | Sep 24 08:25:29 PM UTC 24 |
| Peak memory | 227204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345428788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1345428788 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.2824689249 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 65785331 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 08:25:30 PM UTC 24 |
| Finished | Sep 24 08:25:33 PM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824689249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2824689249 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.1859751366 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 130401531614 ps |
| CPU time | 2988.14 seconds |
| Started | Sep 24 08:23:57 PM UTC 24 |
| Finished | Sep 24 09:14:22 PM UTC 24 |
| Peak memory | 3275564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859751366 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.1859751366 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.3184477733 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 24861304505 ps |
| CPU time | 412.5 seconds |
| Started | Sep 24 08:23:58 PM UTC 24 |
| Finished | Sep 24 08:30:56 PM UTC 24 |
| Peak memory | 555828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184477733 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3184477733 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.547686575 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 130432805 ps |
| CPU time | 2.87 seconds |
| Started | Sep 24 08:23:55 PM UTC 24 |
| Finished | Sep 24 08:23:59 PM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547686575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.547686575 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.4223969354 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 40720354714 ps |
| CPU time | 1236.87 seconds |
| Started | Sep 24 08:25:30 PM UTC 24 |
| Finished | Sep 24 08:46:25 PM UTC 24 |
| Peak memory | 1041564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223969354 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.4223969354 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.1471047716 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 20426434 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:28:02 PM UTC 24 |
| Finished | Sep 24 08:28:05 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471047716 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1471047716 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.792899107 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 16564437986 ps |
| CPU time | 124.87 seconds |
| Started | Sep 24 08:26:20 PM UTC 24 |
| Finished | Sep 24 08:28:28 PM UTC 24 |
| Peak memory | 310056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792899107 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.792899107 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.3341644024 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 14194820677 ps |
| CPU time | 333.62 seconds |
| Started | Sep 24 08:26:17 PM UTC 24 |
| Finished | Sep 24 08:31:56 PM UTC 24 |
| Peak memory | 242428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341644024 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3341644024 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.1415397624 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 236168630 ps |
| CPU time | 23.77 seconds |
| Started | Sep 24 08:27:23 PM UTC 24 |
| Finished | Sep 24 08:27:48 PM UTC 24 |
| Peak memory | 233868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415397624 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1415397624 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.2785482168 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 321394200 ps |
| CPU time | 3.78 seconds |
| Started | Sep 24 08:27:28 PM UTC 24 |
| Finished | Sep 24 08:27:33 PM UTC 24 |
| Peak memory | 227264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785482168 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2785482168 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.1340475913 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 8771438533 ps |
| CPU time | 90 seconds |
| Started | Sep 24 08:26:33 PM UTC 24 |
| Finished | Sep 24 08:28:05 PM UTC 24 |
| Peak memory | 285684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340475913 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1340475913 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.550069544 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 65863268188 ps |
| CPU time | 490.39 seconds |
| Started | Sep 24 08:27:12 PM UTC 24 |
| Finished | Sep 24 08:35:29 PM UTC 24 |
| Peak memory | 611064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550069544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.550069544 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.4150134949 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 742391403 ps |
| CPU time | 2.83 seconds |
| Started | Sep 24 08:27:18 PM UTC 24 |
| Finished | Sep 24 08:27:22 PM UTC 24 |
| Peak memory | 227168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150134949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.4150134949 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.3945999070 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 2674128253 ps |
| CPU time | 25.69 seconds |
| Started | Sep 24 08:27:34 PM UTC 24 |
| Finished | Sep 24 08:28:01 PM UTC 24 |
| Peak memory | 250648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945999070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3945999070 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1287948130 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 17591020328 ps |
| CPU time | 2029.81 seconds |
| Started | Sep 24 08:25:35 PM UTC 24 |
| Finished | Sep 24 08:59:51 PM UTC 24 |
| Peak memory | 1239856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287948130 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1287948130 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.1388714450 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 28719482623 ps |
| CPU time | 486.5 seconds |
| Started | Sep 24 08:25:35 PM UTC 24 |
| Finished | Sep 24 08:33:48 PM UTC 24 |
| Peak memory | 607288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388714450 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1388714450 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.2463317998 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4169282957 ps |
| CPU time | 101.04 seconds |
| Started | Sep 24 08:25:33 PM UTC 24 |
| Finished | Sep 24 08:27:17 PM UTC 24 |
| Peak memory | 234524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463317998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2463317998 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.2599033317 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 8883417830 ps |
| CPU time | 333.98 seconds |
| Started | Sep 24 08:27:49 PM UTC 24 |
| Finished | Sep 24 08:33:28 PM UTC 24 |
| Peak memory | 447600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599033317 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2599033317 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.4231602591 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 18074018 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:29:29 PM UTC 24 |
| Finished | Sep 24 08:29:31 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231602591 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.4231602591 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.3716941580 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 6475870376 ps |
| CPU time | 241.44 seconds |
| Started | Sep 24 08:28:29 PM UTC 24 |
| Finished | Sep 24 08:32:34 PM UTC 24 |
| Peak memory | 371504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716941580 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3716941580 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.1940766819 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1897101617 ps |
| CPU time | 49.1 seconds |
| Started | Sep 24 08:28:27 PM UTC 24 |
| Finished | Sep 24 08:29:17 PM UTC 24 |
| Peak memory | 233644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940766819 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1940766819 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.3410219042 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 30779638091 ps |
| CPU time | 53.26 seconds |
| Started | Sep 24 08:29:08 PM UTC 24 |
| Finished | Sep 24 08:30:03 PM UTC 24 |
| Peak memory | 234188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410219042 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3410219042 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.859839187 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 504562220 ps |
| CPU time | 24.74 seconds |
| Started | Sep 24 08:29:19 PM UTC 24 |
| Finished | Sep 24 08:29:45 PM UTC 24 |
| Peak memory | 233552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859839187 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.859839187 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.3882247487 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 244787471523 ps |
| CPU time | 518.23 seconds |
| Started | Sep 24 08:28:36 PM UTC 24 |
| Finished | Sep 24 08:37:22 PM UTC 24 |
| Peak memory | 482104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882247487 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3882247487 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.1531634797 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 11572463435 ps |
| CPU time | 218.83 seconds |
| Started | Sep 24 08:28:46 PM UTC 24 |
| Finished | Sep 24 08:32:29 PM UTC 24 |
| Peak memory | 316276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531634797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1531634797 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.2733623333 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 10565133869 ps |
| CPU time | 13.94 seconds |
| Started | Sep 24 08:28:52 PM UTC 24 |
| Finished | Sep 24 08:29:08 PM UTC 24 |
| Peak memory | 227396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733623333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2733623333 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.1376515205 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 106524098 ps |
| CPU time | 2.13 seconds |
| Started | Sep 24 08:29:20 PM UTC 24 |
| Finished | Sep 24 08:29:23 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376515205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1376515205 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.4182753919 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 109861665055 ps |
| CPU time | 4041.39 seconds |
| Started | Sep 24 08:28:06 PM UTC 24 |
| Finished | Sep 24 09:36:13 PM UTC 24 |
| Peak memory | 4174744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182753919 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.4182753919 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.842613782 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 32046177771 ps |
| CPU time | 356.09 seconds |
| Started | Sep 24 08:28:17 PM UTC 24 |
| Finished | Sep 24 08:34:17 PM UTC 24 |
| Peak memory | 580400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842613782 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.842613782 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.2623522147 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1629812143 ps |
| CPU time | 28.01 seconds |
| Started | Sep 24 08:28:05 PM UTC 24 |
| Finished | Sep 24 08:28:35 PM UTC 24 |
| Peak memory | 231572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623522147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2623522147 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.2257019785 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6277535426 ps |
| CPU time | 565.99 seconds |
| Started | Sep 24 08:29:24 PM UTC 24 |
| Finished | Sep 24 08:38:58 PM UTC 24 |
| Peak memory | 351440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257019785 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.2257019785 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.168924246 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 32341783 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:03:18 PM UTC 24 |
| Finished | Sep 24 08:03:21 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168924246 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.168924246 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.740729580 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 4009661880 ps |
| CPU time | 115.02 seconds |
| Started | Sep 24 08:02:22 PM UTC 24 |
| Finished | Sep 24 08:04:20 PM UTC 24 |
| Peak memory | 308140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740729580 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.740729580 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.3493371525 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 7576362469 ps |
| CPU time | 293.16 seconds |
| Started | Sep 24 08:02:24 PM UTC 24 |
| Finished | Sep 24 08:07:22 PM UTC 24 |
| Peak memory | 334816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493371525 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3493371525 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.3488670084 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 135674983157 ps |
| CPU time | 1279.57 seconds |
| Started | Sep 24 08:01:43 PM UTC 24 |
| Finished | Sep 24 08:23:18 PM UTC 24 |
| Peak memory | 273464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488670084 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3488670084 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2055333755 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 328121092 ps |
| CPU time | 13.72 seconds |
| Started | Sep 24 08:03:02 PM UTC 24 |
| Finished | Sep 24 08:03:17 PM UTC 24 |
| Peak memory | 231268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055333755 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2055333755 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.1932194591 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4612348591 ps |
| CPU time | 29.61 seconds |
| Started | Sep 24 08:03:02 PM UTC 24 |
| Finished | Sep 24 08:03:33 PM UTC 24 |
| Peak memory | 234000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932194591 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1932194591 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.1586900292 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 6876523495 ps |
| CPU time | 73.16 seconds |
| Started | Sep 24 08:03:02 PM UTC 24 |
| Finished | Sep 24 08:04:17 PM UTC 24 |
| Peak memory | 234344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586900292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1586900292 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.2730363084 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 56634925509 ps |
| CPU time | 289.26 seconds |
| Started | Sep 24 08:02:25 PM UTC 24 |
| Finished | Sep 24 08:07:18 PM UTC 24 |
| Peak memory | 441208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730363084 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.2730363084 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.236706319 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3412799414 ps |
| CPU time | 118.25 seconds |
| Started | Sep 24 08:02:42 PM UTC 24 |
| Finished | Sep 24 08:04:43 PM UTC 24 |
| Peak memory | 328528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236706319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.236706319 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.4157293194 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1506381016 ps |
| CPU time | 9.86 seconds |
| Started | Sep 24 08:03:01 PM UTC 24 |
| Finished | Sep 24 08:03:12 PM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157293194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.4157293194 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.598296918 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 145557763 ps |
| CPU time | 1.62 seconds |
| Started | Sep 24 08:03:05 PM UTC 24 |
| Finished | Sep 24 08:03:07 PM UTC 24 |
| Peak memory | 226384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598296918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.598296918 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.3437135216 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 66964258532 ps |
| CPU time | 2009.96 seconds |
| Started | Sep 24 08:01:39 PM UTC 24 |
| Finished | Sep 24 08:35:32 PM UTC 24 |
| Peak memory | 2540344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437135216 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.3437135216 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.2652806845 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10645944623 ps |
| CPU time | 259.45 seconds |
| Started | Sep 24 08:02:31 PM UTC 24 |
| Finished | Sep 24 08:06:55 PM UTC 24 |
| Peak memory | 404576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652806845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.2652806845 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.1442494833 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2981961066 ps |
| CPU time | 45.13 seconds |
| Started | Sep 24 08:03:15 PM UTC 24 |
| Finished | Sep 24 08:04:02 PM UTC 24 |
| Peak memory | 274568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442494833 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1442494833 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.1162814060 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 964995526 ps |
| CPU time | 28.36 seconds |
| Started | Sep 24 08:01:41 PM UTC 24 |
| Finished | Sep 24 08:02:11 PM UTC 24 |
| Peak memory | 234160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162814060 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1162814060 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.1341611813 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 116570755 ps |
| CPU time | 1.75 seconds |
| Started | Sep 24 08:01:39 PM UTC 24 |
| Finished | Sep 24 08:01:41 PM UTC 24 |
| Peak memory | 226296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341611813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.1341611813 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.518268486 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 17900889239 ps |
| CPU time | 169.57 seconds |
| Started | Sep 24 08:03:08 PM UTC 24 |
| Finished | Sep 24 08:06:00 PM UTC 24 |
| Peak memory | 416860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518268486 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.518268486 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.3761560915 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 72895078 ps |
| CPU time | 2.78 seconds |
| Started | Sep 24 08:02:20 PM UTC 24 |
| Finished | Sep 24 08:02:24 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761560915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.3761560915 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.3317649219 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 106324606 ps |
| CPU time | 2.4 seconds |
| Started | Sep 24 08:02:20 PM UTC 24 |
| Finished | Sep 24 08:02:24 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317649219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3317649219 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.3753260853 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1815513176 ps |
| CPU time | 65.21 seconds |
| Started | Sep 24 08:01:53 PM UTC 24 |
| Finished | Sep 24 08:03:00 PM UTC 24 |
| Peak memory | 256560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753260853 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3753260853 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.2915037302 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1682300718 ps |
| CPU time | 60.05 seconds |
| Started | Sep 24 08:02:01 PM UTC 24 |
| Finished | Sep 24 08:03:03 PM UTC 24 |
| Peak memory | 250480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915037302 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.2915037302 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.3847676950 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 517193949 ps |
| CPU time | 24.63 seconds |
| Started | Sep 24 08:02:04 PM UTC 24 |
| Finished | Sep 24 08:02:29 PM UTC 24 |
| Peak memory | 233568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847676950 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3847676950 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.3223836831 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 41818827926 ps |
| CPU time | 1236.59 seconds |
| Started | Sep 24 08:02:19 PM UTC 24 |
| Finished | Sep 24 08:23:11 PM UTC 24 |
| Peak memory | 1698456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223836831 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3223836831 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.1631035399 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 71593505533 ps |
| CPU time | 3012.47 seconds |
| Started | Sep 24 08:02:19 PM UTC 24 |
| Finished | Sep 24 08:53:06 PM UTC 24 |
| Peak memory | 3666584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631035399 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1631035 399 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.3396158934 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 244663447991 ps |
| CPU time | 2326.44 seconds |
| Started | Sep 24 08:02:20 PM UTC 24 |
| Finished | Sep 24 08:41:33 PM UTC 24 |
| Peak memory | 3039888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396158934 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3396158 934 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.916422358 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 27393314 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:31:12 PM UTC 24 |
| Finished | Sep 24 08:31:14 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916422358 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.916422358 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.825631925 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2110694406 ps |
| CPU time | 31.31 seconds |
| Started | Sep 24 08:30:04 PM UTC 24 |
| Finished | Sep 24 08:30:37 PM UTC 24 |
| Peak memory | 236404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825631925 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.825631925 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.163835214 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 47497545076 ps |
| CPU time | 908.26 seconds |
| Started | Sep 24 08:29:55 PM UTC 24 |
| Finished | Sep 24 08:45:15 PM UTC 24 |
| Peak memory | 260848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163835214 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.163835214 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.4184920070 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 10916400404 ps |
| CPU time | 253.61 seconds |
| Started | Sep 24 08:30:19 PM UTC 24 |
| Finished | Sep 24 08:34:37 PM UTC 24 |
| Peak memory | 412464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184920070 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.4184920070 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.3019557595 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 25271852885 ps |
| CPU time | 204.26 seconds |
| Started | Sep 24 08:30:38 PM UTC 24 |
| Finished | Sep 24 08:34:05 PM UTC 24 |
| Peak memory | 320372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019557595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3019557595 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.908609698 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1649399161 ps |
| CPU time | 6.13 seconds |
| Started | Sep 24 08:30:57 PM UTC 24 |
| Finished | Sep 24 08:31:04 PM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908609698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.908609698 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.1414500655 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 164080686 ps |
| CPU time | 2.08 seconds |
| Started | Sep 24 08:31:05 PM UTC 24 |
| Finished | Sep 24 08:31:08 PM UTC 24 |
| Peak memory | 227368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414500655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1414500655 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.509686105 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 88763072425 ps |
| CPU time | 2377.49 seconds |
| Started | Sep 24 08:29:38 PM UTC 24 |
| Finished | Sep 24 09:09:43 PM UTC 24 |
| Peak memory | 1657652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509686105 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.509686105 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.2421649263 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4324177723 ps |
| CPU time | 317.52 seconds |
| Started | Sep 24 08:29:45 PM UTC 24 |
| Finished | Sep 24 08:35:07 PM UTC 24 |
| Peak memory | 359220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421649263 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.2421649263 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.2592222331 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 420753788 ps |
| CPU time | 3.93 seconds |
| Started | Sep 24 08:29:32 PM UTC 24 |
| Finished | Sep 24 08:29:37 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592222331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.2592222331 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.4181079545 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 114652476302 ps |
| CPU time | 1633.17 seconds |
| Started | Sep 24 08:31:09 PM UTC 24 |
| Finished | Sep 24 08:58:42 PM UTC 24 |
| Peak memory | 1102940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181079545 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.4181079545 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.3414410172 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 64724981 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:32:45 PM UTC 24 |
| Finished | Sep 24 08:32:48 PM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414410172 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3414410172 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.1332319191 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 113947026101 ps |
| CPU time | 321.96 seconds |
| Started | Sep 24 08:31:55 PM UTC 24 |
| Finished | Sep 24 08:37:22 PM UTC 24 |
| Peak memory | 486136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332319191 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1332319191 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.3276407614 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 48520434121 ps |
| CPU time | 1207.48 seconds |
| Started | Sep 24 08:31:43 PM UTC 24 |
| Finished | Sep 24 08:52:08 PM UTC 24 |
| Peak memory | 267360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276407614 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3276407614 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.3975948574 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3611988080 ps |
| CPU time | 41.43 seconds |
| Started | Sep 24 08:31:57 PM UTC 24 |
| Finished | Sep 24 08:32:40 PM UTC 24 |
| Peak memory | 244576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975948574 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.3975948574 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.2489348737 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 10519738440 ps |
| CPU time | 388.9 seconds |
| Started | Sep 24 08:32:30 PM UTC 24 |
| Finished | Sep 24 08:39:05 PM UTC 24 |
| Peak memory | 537592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489348737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2489348737 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.637436479 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 847644931 ps |
| CPU time | 6.9 seconds |
| Started | Sep 24 08:32:35 PM UTC 24 |
| Finished | Sep 24 08:32:43 PM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637436479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.637436479 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.21079593 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 33633981 ps |
| CPU time | 1.99 seconds |
| Started | Sep 24 08:32:41 PM UTC 24 |
| Finished | Sep 24 08:32:44 PM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21079593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.21079593 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.3250722470 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 19044519193 ps |
| CPU time | 458.02 seconds |
| Started | Sep 24 08:31:21 PM UTC 24 |
| Finished | Sep 24 08:39:06 PM UTC 24 |
| Peak memory | 515152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250722470 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.3250722470 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.628807227 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 33173014073 ps |
| CPU time | 405.74 seconds |
| Started | Sep 24 08:31:26 PM UTC 24 |
| Finished | Sep 24 08:38:18 PM UTC 24 |
| Peak memory | 560052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628807227 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.628807227 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.27165944 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1566591598 ps |
| CPU time | 26.16 seconds |
| Started | Sep 24 08:31:15 PM UTC 24 |
| Finished | Sep 24 08:31:42 PM UTC 24 |
| Peak memory | 233680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27165944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.27165944 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.4120656524 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 31388638342 ps |
| CPU time | 816.64 seconds |
| Started | Sep 24 08:32:44 PM UTC 24 |
| Finished | Sep 24 08:46:33 PM UTC 24 |
| Peak memory | 627872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120656524 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.4120656524 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.492904038 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 21154955 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:34:19 PM UTC 24 |
| Finished | Sep 24 08:34:21 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492904038 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.492904038 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.472851022 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 667436010 ps |
| CPU time | 33.27 seconds |
| Started | Sep 24 08:33:43 PM UTC 24 |
| Finished | Sep 24 08:34:18 PM UTC 24 |
| Peak memory | 238388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472851022 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.472851022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.1833043672 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 6331843894 ps |
| CPU time | 73.87 seconds |
| Started | Sep 24 08:33:34 PM UTC 24 |
| Finished | Sep 24 08:34:50 PM UTC 24 |
| Peak memory | 234296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833043672 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1833043672 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.3062564534 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 4694035397 ps |
| CPU time | 80.8 seconds |
| Started | Sep 24 08:33:49 PM UTC 24 |
| Finished | Sep 24 08:35:12 PM UTC 24 |
| Peak memory | 295992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062564534 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3062564534 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.831490077 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1397080921 ps |
| CPU time | 4.72 seconds |
| Started | Sep 24 08:34:06 PM UTC 24 |
| Finished | Sep 24 08:34:12 PM UTC 24 |
| Peak memory | 227172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831490077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.831490077 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.2729690520 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 137064079 ps |
| CPU time | 5.06 seconds |
| Started | Sep 24 08:34:13 PM UTC 24 |
| Finished | Sep 24 08:34:20 PM UTC 24 |
| Peak memory | 231796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729690520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2729690520 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.2432727792 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 116592945406 ps |
| CPU time | 1914.33 seconds |
| Started | Sep 24 08:33:12 PM UTC 24 |
| Finished | Sep 24 09:05:31 PM UTC 24 |
| Peak memory | 1231640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432727792 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.2432727792 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.644926176 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 15872913641 ps |
| CPU time | 408.58 seconds |
| Started | Sep 24 08:33:33 PM UTC 24 |
| Finished | Sep 24 08:40:28 PM UTC 24 |
| Peak memory | 377652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644926176 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.644926176 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.1632634181 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 990228798 ps |
| CPU time | 20.57 seconds |
| Started | Sep 24 08:32:48 PM UTC 24 |
| Finished | Sep 24 08:33:10 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632634181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1632634181 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.683975282 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 103927872 ps |
| CPU time | 3.69 seconds |
| Started | Sep 24 08:34:19 PM UTC 24 |
| Finished | Sep 24 08:34:24 PM UTC 24 |
| Peak memory | 229480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683975282 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.683975282 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.2264212163 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 24703273 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:35:17 PM UTC 24 |
| Finished | Sep 24 08:35:19 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264212163 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2264212163 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.1639178346 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 6430277581 ps |
| CPU time | 122.33 seconds |
| Started | Sep 24 08:34:43 PM UTC 24 |
| Finished | Sep 24 08:36:48 PM UTC 24 |
| Peak memory | 277292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639178346 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1639178346 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.1198285656 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 4189973045 ps |
| CPU time | 217.39 seconds |
| Started | Sep 24 08:34:42 PM UTC 24 |
| Finished | Sep 24 08:38:23 PM UTC 24 |
| Peak memory | 238392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198285656 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.1198285656 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.834287930 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 10946715607 ps |
| CPU time | 96.12 seconds |
| Started | Sep 24 08:34:45 PM UTC 24 |
| Finished | Sep 24 08:36:23 PM UTC 24 |
| Peak memory | 271192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834287930 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.834287930 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.4054357964 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 6728286961 ps |
| CPU time | 336.82 seconds |
| Started | Sep 24 08:34:50 PM UTC 24 |
| Finished | Sep 24 08:40:32 PM UTC 24 |
| Peak memory | 357104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054357964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.4054357964 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.1732207459 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 580503164 ps |
| CPU time | 6.68 seconds |
| Started | Sep 24 08:35:08 PM UTC 24 |
| Finished | Sep 24 08:35:16 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732207459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1732207459 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.556817009 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 46885284 ps |
| CPU time | 1.97 seconds |
| Started | Sep 24 08:35:12 PM UTC 24 |
| Finished | Sep 24 08:35:15 PM UTC 24 |
| Peak memory | 226328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556817009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.556817009 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.2160678793 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 230177522280 ps |
| CPU time | 3875.94 seconds |
| Started | Sep 24 08:34:22 PM UTC 24 |
| Finished | Sep 24 09:39:41 PM UTC 24 |
| Peak memory | 4322192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160678793 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.2160678793 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.578552083 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 76560567540 ps |
| CPU time | 418.04 seconds |
| Started | Sep 24 08:34:25 PM UTC 24 |
| Finished | Sep 24 08:41:29 PM UTC 24 |
| Peak memory | 568160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578552083 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.578552083 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.2075398579 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 729031572 ps |
| CPU time | 22.17 seconds |
| Started | Sep 24 08:34:21 PM UTC 24 |
| Finished | Sep 24 08:34:44 PM UTC 24 |
| Peak memory | 231596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075398579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.2075398579 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.4205008565 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 189021147474 ps |
| CPU time | 616.38 seconds |
| Started | Sep 24 08:35:17 PM UTC 24 |
| Finished | Sep 24 08:45:41 PM UTC 24 |
| Peak memory | 449724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205008565 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.4205008565 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.1063741387 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 76739880 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:36:22 PM UTC 24 |
| Finished | Sep 24 08:36:24 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063741387 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.1063741387 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.3605520693 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 4717650212 ps |
| CPU time | 314.55 seconds |
| Started | Sep 24 08:35:33 PM UTC 24 |
| Finished | Sep 24 08:40:52 PM UTC 24 |
| Peak memory | 346928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605520693 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3605520693 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.2555481997 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 32670992469 ps |
| CPU time | 1010.46 seconds |
| Started | Sep 24 08:35:30 PM UTC 24 |
| Finished | Sep 24 08:52:34 PM UTC 24 |
| Peak memory | 250656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555481997 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.2555481997 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1932402741 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 19976308218 ps |
| CPU time | 178.52 seconds |
| Started | Sep 24 08:35:45 PM UTC 24 |
| Finished | Sep 24 08:38:47 PM UTC 24 |
| Peak memory | 304184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932402741 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1932402741 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.2801654006 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 6732086700 ps |
| CPU time | 150.7 seconds |
| Started | Sep 24 08:35:50 PM UTC 24 |
| Finished | Sep 24 08:38:24 PM UTC 24 |
| Peak memory | 373548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801654006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2801654006 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.2699343916 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 522912109 ps |
| CPU time | 6.29 seconds |
| Started | Sep 24 08:36:13 PM UTC 24 |
| Finished | Sep 24 08:36:21 PM UTC 24 |
| Peak memory | 227200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699343916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2699343916 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.3630402093 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 36931549 ps |
| CPU time | 1.97 seconds |
| Started | Sep 24 08:36:15 PM UTC 24 |
| Finished | Sep 24 08:36:18 PM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630402093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.3630402093 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.1244361387 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1238070151 ps |
| CPU time | 51.34 seconds |
| Started | Sep 24 08:35:20 PM UTC 24 |
| Finished | Sep 24 08:36:13 PM UTC 24 |
| Peak memory | 254628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244361387 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.1244361387 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.134688501 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2717192736 ps |
| CPU time | 56.73 seconds |
| Started | Sep 24 08:35:30 PM UTC 24 |
| Finished | Sep 24 08:36:29 PM UTC 24 |
| Peak memory | 250720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134688501 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.134688501 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.2349897493 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 427927418 ps |
| CPU time | 28.5 seconds |
| Started | Sep 24 08:35:20 PM UTC 24 |
| Finished | Sep 24 08:35:50 PM UTC 24 |
| Peak memory | 231124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349897493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2349897493 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.461922417 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 43896159214 ps |
| CPU time | 904.14 seconds |
| Started | Sep 24 08:36:19 PM UTC 24 |
| Finished | Sep 24 08:51:36 PM UTC 24 |
| Peak memory | 736276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461922417 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.461922417 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.1218127028 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 16823396 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:37:36 PM UTC 24 |
| Finished | Sep 24 08:37:38 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218127028 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1218127028 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.3096268020 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1132567450 ps |
| CPU time | 41.46 seconds |
| Started | Sep 24 08:36:48 PM UTC 24 |
| Finished | Sep 24 08:37:31 PM UTC 24 |
| Peak memory | 244404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096268020 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3096268020 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.1871478485 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 9606571046 ps |
| CPU time | 332.43 seconds |
| Started | Sep 24 08:36:40 PM UTC 24 |
| Finished | Sep 24 08:42:17 PM UTC 24 |
| Peak memory | 242484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871478485 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1871478485 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.2295618292 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 7053915872 ps |
| CPU time | 75 seconds |
| Started | Sep 24 08:36:55 PM UTC 24 |
| Finished | Sep 24 08:38:12 PM UTC 24 |
| Peak memory | 283480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295618292 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2295618292 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.3499868343 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 112260196627 ps |
| CPU time | 397.36 seconds |
| Started | Sep 24 08:37:23 PM UTC 24 |
| Finished | Sep 24 08:44:05 PM UTC 24 |
| Peak memory | 574296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499868343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3499868343 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.749182263 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2556681871 ps |
| CPU time | 11.02 seconds |
| Started | Sep 24 08:37:23 PM UTC 24 |
| Finished | Sep 24 08:37:35 PM UTC 24 |
| Peak memory | 227300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749182263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.749182263 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.1345164744 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 138401927 ps |
| CPU time | 1.94 seconds |
| Started | Sep 24 08:37:32 PM UTC 24 |
| Finished | Sep 24 08:37:35 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345164744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1345164744 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.3378662224 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 11477279740 ps |
| CPU time | 227.74 seconds |
| Started | Sep 24 08:36:25 PM UTC 24 |
| Finished | Sep 24 08:40:16 PM UTC 24 |
| Peak memory | 514832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378662224 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.3378662224 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.3766492512 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 26255253477 ps |
| CPU time | 187.07 seconds |
| Started | Sep 24 08:36:29 PM UTC 24 |
| Finished | Sep 24 08:39:39 PM UTC 24 |
| Peak memory | 371448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766492512 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3766492512 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.711845554 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3258219682 ps |
| CPU time | 13.92 seconds |
| Started | Sep 24 08:36:24 PM UTC 24 |
| Finished | Sep 24 08:36:39 PM UTC 24 |
| Peak memory | 231656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711845554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.711845554 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.3286594107 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 125125067417 ps |
| CPU time | 1471.57 seconds |
| Started | Sep 24 08:37:36 PM UTC 24 |
| Finished | Sep 24 09:02:26 PM UTC 24 |
| Peak memory | 535640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286594107 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3286594107 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.1013776775 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 60722817 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:38:55 PM UTC 24 |
| Finished | Sep 24 08:38:57 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013776775 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1013776775 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_app.2939827009 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 923989507 ps |
| CPU time | 29.73 seconds |
| Started | Sep 24 08:38:24 PM UTC 24 |
| Finished | Sep 24 08:38:55 PM UTC 24 |
| Peak memory | 238256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939827009 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2939827009 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.177878666 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 32511455494 ps |
| CPU time | 1160.89 seconds |
| Started | Sep 24 08:38:19 PM UTC 24 |
| Finished | Sep 24 08:57:56 PM UTC 24 |
| Peak memory | 267048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177878666 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.177878666 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.1661457282 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 38758271047 ps |
| CPU time | 233 seconds |
| Started | Sep 24 08:38:24 PM UTC 24 |
| Finished | Sep 24 08:42:20 PM UTC 24 |
| Peak memory | 424824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661457282 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1661457282 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.1505944625 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 21253101462 ps |
| CPU time | 427 seconds |
| Started | Sep 24 08:38:25 PM UTC 24 |
| Finished | Sep 24 08:45:38 PM UTC 24 |
| Peak memory | 627500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505944625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1505944625 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.4137020187 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 4340662748 ps |
| CPU time | 9.49 seconds |
| Started | Sep 24 08:38:46 PM UTC 24 |
| Finished | Sep 24 08:38:56 PM UTC 24 |
| Peak memory | 227356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137020187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.4137020187 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.1871919127 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 207296919 ps |
| CPU time | 2.03 seconds |
| Started | Sep 24 08:38:48 PM UTC 24 |
| Finished | Sep 24 08:38:51 PM UTC 24 |
| Peak memory | 227660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871919127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1871919127 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.1248316725 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 40925280163 ps |
| CPU time | 2179.95 seconds |
| Started | Sep 24 08:37:39 PM UTC 24 |
| Finished | Sep 24 09:14:27 PM UTC 24 |
| Peak memory | 1528556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248316725 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.1248316725 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.1232741464 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 15451593911 ps |
| CPU time | 285.14 seconds |
| Started | Sep 24 08:38:13 PM UTC 24 |
| Finished | Sep 24 08:43:03 PM UTC 24 |
| Peak memory | 502616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232741464 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1232741464 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.2249402647 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3342343305 ps |
| CPU time | 45.21 seconds |
| Started | Sep 24 08:37:36 PM UTC 24 |
| Finished | Sep 24 08:38:23 PM UTC 24 |
| Peak memory | 234552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249402647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2249402647 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/26.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.3960619176 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 21569133 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 08:39:40 PM UTC 24 |
| Finished | Sep 24 08:39:42 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960619176 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3960619176 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.517524983 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 10006598530 ps |
| CPU time | 309.08 seconds |
| Started | Sep 24 08:39:06 PM UTC 24 |
| Finished | Sep 24 08:44:20 PM UTC 24 |
| Peak memory | 453484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517524983 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.517524983 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.1993602384 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 29720974968 ps |
| CPU time | 346.51 seconds |
| Started | Sep 24 08:39:01 PM UTC 24 |
| Finished | Sep 24 08:44:53 PM UTC 24 |
| Peak memory | 238392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993602384 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1993602384 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.1420856000 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 8664381398 ps |
| CPU time | 196.95 seconds |
| Started | Sep 24 08:39:07 PM UTC 24 |
| Finished | Sep 24 08:42:27 PM UTC 24 |
| Peak memory | 336952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420856000 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1420856000 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.769117916 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 193072777762 ps |
| CPU time | 527.7 seconds |
| Started | Sep 24 08:39:11 PM UTC 24 |
| Finished | Sep 24 08:48:06 PM UTC 24 |
| Peak memory | 662260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769117916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.769117916 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.931245788 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 10630081183 ps |
| CPU time | 17.13 seconds |
| Started | Sep 24 08:39:23 PM UTC 24 |
| Finished | Sep 24 08:39:41 PM UTC 24 |
| Peak memory | 227404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931245788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.931245788 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.875303479 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 63321550 ps |
| CPU time | 3.59 seconds |
| Started | Sep 24 08:39:24 PM UTC 24 |
| Finished | Sep 24 08:39:29 PM UTC 24 |
| Peak memory | 229596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875303479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.875303479 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.4213379741 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 99613937478 ps |
| CPU time | 3342.87 seconds |
| Started | Sep 24 08:38:58 PM UTC 24 |
| Finished | Sep 24 09:35:20 PM UTC 24 |
| Peak memory | 3762988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213379741 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.4213379741 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.3975788664 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 60744493497 ps |
| CPU time | 404.39 seconds |
| Started | Sep 24 08:38:58 PM UTC 24 |
| Finished | Sep 24 08:45:49 PM UTC 24 |
| Peak memory | 525364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975788664 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3975788664 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.856599307 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 810623918 ps |
| CPU time | 25.04 seconds |
| Started | Sep 24 08:38:57 PM UTC 24 |
| Finished | Sep 24 08:39:24 PM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856599307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.856599307 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.3166660738 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 42704310032 ps |
| CPU time | 551.65 seconds |
| Started | Sep 24 08:39:29 PM UTC 24 |
| Finished | Sep 24 08:48:49 PM UTC 24 |
| Peak memory | 509012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166660738 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3166660738 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.3987906062 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 17726781 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:41:10 PM UTC 24 |
| Finished | Sep 24 08:41:12 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987906062 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3987906062 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.3831186009 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1480572790 ps |
| CPU time | 74.55 seconds |
| Started | Sep 24 08:40:29 PM UTC 24 |
| Finished | Sep 24 08:41:46 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831186009 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3831186009 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.792884024 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 66206445940 ps |
| CPU time | 1211.68 seconds |
| Started | Sep 24 08:40:25 PM UTC 24 |
| Finished | Sep 24 09:00:52 PM UTC 24 |
| Peak memory | 266992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792884024 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.792884024 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.342298230 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 5537207258 ps |
| CPU time | 226.06 seconds |
| Started | Sep 24 08:40:33 PM UTC 24 |
| Finished | Sep 24 08:44:23 PM UTC 24 |
| Peak memory | 322612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342298230 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.342298230 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.2876396661 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 16865563429 ps |
| CPU time | 173.64 seconds |
| Started | Sep 24 08:40:47 PM UTC 24 |
| Finished | Sep 24 08:43:44 PM UTC 24 |
| Peak memory | 312088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876396661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.2876396661 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.1794664249 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 466042314 ps |
| CPU time | 5.89 seconds |
| Started | Sep 24 08:40:53 PM UTC 24 |
| Finished | Sep 24 08:41:00 PM UTC 24 |
| Peak memory | 227268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794664249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1794664249 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.4245540309 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 232902977 ps |
| CPU time | 2.13 seconds |
| Started | Sep 24 08:41:02 PM UTC 24 |
| Finished | Sep 24 08:41:05 PM UTC 24 |
| Peak memory | 227660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245540309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.4245540309 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.2478404511 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 249753999589 ps |
| CPU time | 1771.29 seconds |
| Started | Sep 24 08:39:43 PM UTC 24 |
| Finished | Sep 24 09:09:35 PM UTC 24 |
| Peak memory | 2327336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478404511 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.2478404511 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.2431860206 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 12930234565 ps |
| CPU time | 358.81 seconds |
| Started | Sep 24 08:40:18 PM UTC 24 |
| Finished | Sep 24 08:46:22 PM UTC 24 |
| Peak memory | 347228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431860206 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2431860206 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.2303044784 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2938656141 ps |
| CPU time | 62 seconds |
| Started | Sep 24 08:39:42 PM UTC 24 |
| Finished | Sep 24 08:40:46 PM UTC 24 |
| Peak memory | 234260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303044784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.2303044784 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.2876379493 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 14469268552 ps |
| CPU time | 435.06 seconds |
| Started | Sep 24 08:41:06 PM UTC 24 |
| Finished | Sep 24 08:48:27 PM UTC 24 |
| Peak memory | 310424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876379493 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2876379493 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.2232251152 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 16012712 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:42:21 PM UTC 24 |
| Finished | Sep 24 08:42:23 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232251152 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.2232251152 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.2263078018 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 30404412191 ps |
| CPU time | 178 seconds |
| Started | Sep 24 08:41:33 PM UTC 24 |
| Finished | Sep 24 08:44:34 PM UTC 24 |
| Peak memory | 385780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263078018 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2263078018 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.2294336977 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 26378242943 ps |
| CPU time | 680.7 seconds |
| Started | Sep 24 08:41:30 PM UTC 24 |
| Finished | Sep 24 08:53:00 PM UTC 24 |
| Peak memory | 248568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294336977 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2294336977 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.3778860355 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 13280616826 ps |
| CPU time | 331.65 seconds |
| Started | Sep 24 08:41:46 PM UTC 24 |
| Finished | Sep 24 08:47:23 PM UTC 24 |
| Peak memory | 525108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778860355 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3778860355 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.3549352657 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 65969062180 ps |
| CPU time | 393.28 seconds |
| Started | Sep 24 08:41:54 PM UTC 24 |
| Finished | Sep 24 08:48:32 PM UTC 24 |
| Peak memory | 574252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549352657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3549352657 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.4157474600 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 984304125 ps |
| CPU time | 10.97 seconds |
| Started | Sep 24 08:42:04 PM UTC 24 |
| Finished | Sep 24 08:42:16 PM UTC 24 |
| Peak memory | 227164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157474600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.4157474600 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.2013592952 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 77081778432 ps |
| CPU time | 2459.8 seconds |
| Started | Sep 24 08:41:13 PM UTC 24 |
| Finished | Sep 24 09:22:43 PM UTC 24 |
| Peak memory | 2994984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013592952 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.2013592952 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.4159227531 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2900726248 ps |
| CPU time | 45.22 seconds |
| Started | Sep 24 08:41:16 PM UTC 24 |
| Finished | Sep 24 08:42:03 PM UTC 24 |
| Peak memory | 240732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159227531 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.4159227531 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.1084808993 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 561451770 ps |
| CPU time | 40.04 seconds |
| Started | Sep 24 08:41:11 PM UTC 24 |
| Finished | Sep 24 08:41:53 PM UTC 24 |
| Peak memory | 231792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084808993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1084808993 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.2916178595 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 74307986822 ps |
| CPU time | 1216.57 seconds |
| Started | Sep 24 08:42:18 PM UTC 24 |
| Finished | Sep 24 09:02:49 PM UTC 24 |
| Peak memory | 1082776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916178595 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2916178595 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.594992284 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 134976848 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:05:02 PM UTC 24 |
| Finished | Sep 24 08:05:04 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594992284 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.594992284 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.125756124 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1671422023 ps |
| CPU time | 21.13 seconds |
| Started | Sep 24 08:04:21 PM UTC 24 |
| Finished | Sep 24 08:04:43 PM UTC 24 |
| Peak memory | 238452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125756124 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.125756124 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.2463301033 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 6236734622 ps |
| CPU time | 244.66 seconds |
| Started | Sep 24 08:04:26 PM UTC 24 |
| Finished | Sep 24 08:08:34 PM UTC 24 |
| Peak memory | 297836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463301033 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2463301033 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.2804201405 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 655900199 ps |
| CPU time | 15.04 seconds |
| Started | Sep 24 08:04:51 PM UTC 24 |
| Finished | Sep 24 08:05:07 PM UTC 24 |
| Peak memory | 234004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804201405 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2804201405 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.179462972 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3740641429 ps |
| CPU time | 23.19 seconds |
| Started | Sep 24 08:04:51 PM UTC 24 |
| Finished | Sep 24 08:05:15 PM UTC 24 |
| Peak memory | 234316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179462972 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.179462972 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.3799743644 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3343279844 ps |
| CPU time | 17.18 seconds |
| Started | Sep 24 08:04:51 PM UTC 24 |
| Finished | Sep 24 08:05:09 PM UTC 24 |
| Peak memory | 231996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799743644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3799743644 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.3291840050 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 5846861986 ps |
| CPU time | 233.77 seconds |
| Started | Sep 24 08:04:27 PM UTC 24 |
| Finished | Sep 24 08:08:24 PM UTC 24 |
| Peak memory | 302076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291840050 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3291840050 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.3780790485 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3890415515 ps |
| CPU time | 37.19 seconds |
| Started | Sep 24 08:04:42 PM UTC 24 |
| Finished | Sep 24 08:05:21 PM UTC 24 |
| Peak memory | 267284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780790485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3780790485 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.2266212755 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1321358334 ps |
| CPU time | 9.97 seconds |
| Started | Sep 24 08:04:42 PM UTC 24 |
| Finished | Sep 24 08:04:53 PM UTC 24 |
| Peak memory | 227276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266212755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2266212755 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.4225663891 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 42897631 ps |
| CPU time | 1.9 seconds |
| Started | Sep 24 08:04:51 PM UTC 24 |
| Finished | Sep 24 08:04:54 PM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225663891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.4225663891 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.2436958963 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 58083583158 ps |
| CPU time | 3167.97 seconds |
| Started | Sep 24 08:03:36 PM UTC 24 |
| Finished | Sep 24 08:57:02 PM UTC 24 |
| Peak memory | 2005744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436958963 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.2436958963 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.3564241452 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 11562877208 ps |
| CPU time | 142.53 seconds |
| Started | Sep 24 08:04:34 PM UTC 24 |
| Finished | Sep 24 08:06:59 PM UTC 24 |
| Peak memory | 345248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564241452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3564241452 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.812450112 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4842017004 ps |
| CPU time | 39.43 seconds |
| Started | Sep 24 08:05:02 PM UTC 24 |
| Finished | Sep 24 08:05:43 PM UTC 24 |
| Peak memory | 266380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812450112 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.812450112 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.3485013322 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5592845208 ps |
| CPU time | 52.34 seconds |
| Started | Sep 24 08:03:39 PM UTC 24 |
| Finished | Sep 24 08:04:33 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485013322 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3485013322 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.2028551984 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1172432566 ps |
| CPU time | 21.01 seconds |
| Started | Sep 24 08:03:22 PM UTC 24 |
| Finished | Sep 24 08:03:44 PM UTC 24 |
| Peak memory | 229476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028551984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.2028551984 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.757938879 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 277814260 ps |
| CPU time | 3.9 seconds |
| Started | Sep 24 08:04:19 PM UTC 24 |
| Finished | Sep 24 08:04:24 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757938879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.757938879 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.2210533291 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 214962181 ps |
| CPU time | 4.06 seconds |
| Started | Sep 24 08:04:20 PM UTC 24 |
| Finished | Sep 24 08:04:26 PM UTC 24 |
| Peak memory | 229216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210533291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2210533291 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.3568491131 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 10805013799 ps |
| CPU time | 69.24 seconds |
| Started | Sep 24 08:03:47 PM UTC 24 |
| Finished | Sep 24 08:04:58 PM UTC 24 |
| Peak memory | 256724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568491131 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.3568491131 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.2799525505 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1156722073 ps |
| CPU time | 44.88 seconds |
| Started | Sep 24 08:03:58 PM UTC 24 |
| Finished | Sep 24 08:04:45 PM UTC 24 |
| Peak memory | 234136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799525505 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.2799525505 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.589508763 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 190961701087 ps |
| CPU time | 1938.36 seconds |
| Started | Sep 24 08:04:12 PM UTC 24 |
| Finished | Sep 24 08:36:54 PM UTC 24 |
| Peak memory | 2427796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589508763 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.589508763 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.1617085677 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 9729842422 ps |
| CPU time | 818.02 seconds |
| Started | Sep 24 08:04:12 PM UTC 24 |
| Finished | Sep 24 08:18:00 PM UTC 24 |
| Peak memory | 707216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617085677 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1617085677 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.157135440 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 9816487728 ps |
| CPU time | 235.98 seconds |
| Started | Sep 24 08:04:12 PM UTC 24 |
| Finished | Sep 24 08:08:13 PM UTC 24 |
| Peak memory | 441012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157135440 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.15713544 0 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.1524555726 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 230744869101 ps |
| CPU time | 2297.79 seconds |
| Started | Sep 24 08:04:14 PM UTC 24 |
| Finished | Sep 24 08:43:01 PM UTC 24 |
| Peak memory | 2988696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524555726 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1524555 726 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.4200303271 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 22264483 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:43:44 PM UTC 24 |
| Finished | Sep 24 08:43:46 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200303271 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.4200303271 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.833658257 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 11083839127 ps |
| CPU time | 225.21 seconds |
| Started | Sep 24 08:42:37 PM UTC 24 |
| Finished | Sep 24 08:46:26 PM UTC 24 |
| Peak memory | 428848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833658257 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.833658257 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.3255934540 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 15118998588 ps |
| CPU time | 502.03 seconds |
| Started | Sep 24 08:42:28 PM UTC 24 |
| Finished | Sep 24 08:50:57 PM UTC 24 |
| Peak memory | 248568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255934540 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3255934540 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.1794050207 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 10107847007 ps |
| CPU time | 112.28 seconds |
| Started | Sep 24 08:43:03 PM UTC 24 |
| Finished | Sep 24 08:44:57 PM UTC 24 |
| Peak memory | 299816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794050207 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1794050207 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.240288894 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 27733667284 ps |
| CPU time | 375.2 seconds |
| Started | Sep 24 08:43:04 PM UTC 24 |
| Finished | Sep 24 08:49:25 PM UTC 24 |
| Peak memory | 568152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240288894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.240288894 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.779356210 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1238730986 ps |
| CPU time | 12.23 seconds |
| Started | Sep 24 08:43:26 PM UTC 24 |
| Finished | Sep 24 08:43:39 PM UTC 24 |
| Peak memory | 227252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779356210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.779356210 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.2748045674 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 51308692 ps |
| CPU time | 2.64 seconds |
| Started | Sep 24 08:43:40 PM UTC 24 |
| Finished | Sep 24 08:43:44 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748045674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.2748045674 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.3447214908 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 88236372831 ps |
| CPU time | 2978.35 seconds |
| Started | Sep 24 08:42:24 PM UTC 24 |
| Finished | Sep 24 09:32:37 PM UTC 24 |
| Peak memory | 3373804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447214908 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.3447214908 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.481644322 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 665929801 ps |
| CPU time | 6.74 seconds |
| Started | Sep 24 08:42:28 PM UTC 24 |
| Finished | Sep 24 08:42:36 PM UTC 24 |
| Peak memory | 233688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481644322 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.481644322 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.2657400185 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 4025971040 ps |
| CPU time | 62.13 seconds |
| Started | Sep 24 08:42:21 PM UTC 24 |
| Finished | Sep 24 08:43:25 PM UTC 24 |
| Peak memory | 234032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657400185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2657400185 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.3348305613 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 9614274762 ps |
| CPU time | 318.08 seconds |
| Started | Sep 24 08:43:43 PM UTC 24 |
| Finished | Sep 24 08:49:06 PM UTC 24 |
| Peak memory | 316120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348305613 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3348305613 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.2924322390 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 28138351 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:44:54 PM UTC 24 |
| Finished | Sep 24 08:44:57 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924322390 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2924322390 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.1635963382 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 96378686064 ps |
| CPU time | 356.41 seconds |
| Started | Sep 24 08:44:07 PM UTC 24 |
| Finished | Sep 24 08:50:08 PM UTC 24 |
| Peak memory | 504900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635963382 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1635963382 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.2403662834 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 11688491845 ps |
| CPU time | 333.22 seconds |
| Started | Sep 24 08:44:02 PM UTC 24 |
| Finished | Sep 24 08:49:40 PM UTC 24 |
| Peak memory | 238328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403662834 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2403662834 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.1736359912 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 27926715655 ps |
| CPU time | 293.22 seconds |
| Started | Sep 24 08:44:21 PM UTC 24 |
| Finished | Sep 24 08:49:19 PM UTC 24 |
| Peak memory | 457592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736359912 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1736359912 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.3654000927 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 24894596624 ps |
| CPU time | 241.04 seconds |
| Started | Sep 24 08:44:24 PM UTC 24 |
| Finished | Sep 24 08:48:29 PM UTC 24 |
| Peak memory | 396340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654000927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3654000927 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.2124262076 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 6758561559 ps |
| CPU time | 8.84 seconds |
| Started | Sep 24 08:44:35 PM UTC 24 |
| Finished | Sep 24 08:44:45 PM UTC 24 |
| Peak memory | 227372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124262076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2124262076 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.1730581627 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 44595257 ps |
| CPU time | 2.52 seconds |
| Started | Sep 24 08:44:46 PM UTC 24 |
| Finished | Sep 24 08:44:50 PM UTC 24 |
| Peak memory | 229352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730581627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1730581627 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.2945880164 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 43265064311 ps |
| CPU time | 1501.65 seconds |
| Started | Sep 24 08:43:47 PM UTC 24 |
| Finished | Sep 24 09:09:08 PM UTC 24 |
| Peak memory | 1889324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945880164 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.2945880164 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.908768221 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 266008329 ps |
| CPU time | 5.87 seconds |
| Started | Sep 24 08:43:53 PM UTC 24 |
| Finished | Sep 24 08:44:00 PM UTC 24 |
| Peak memory | 231576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908768221 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.908768221 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.686192583 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 691917031 ps |
| CPU time | 6.15 seconds |
| Started | Sep 24 08:43:45 PM UTC 24 |
| Finished | Sep 24 08:43:52 PM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686192583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.686192583 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.3952796596 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 197219736974 ps |
| CPU time | 1439.19 seconds |
| Started | Sep 24 08:44:50 PM UTC 24 |
| Finished | Sep 24 09:09:08 PM UTC 24 |
| Peak memory | 1528884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952796596 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3952796596 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.2214139687 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 20595868 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:46:27 PM UTC 24 |
| Finished | Sep 24 08:46:29 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214139687 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2214139687 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.1974282325 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 13288805961 ps |
| CPU time | 232.77 seconds |
| Started | Sep 24 08:45:39 PM UTC 24 |
| Finished | Sep 24 08:49:36 PM UTC 24 |
| Peak memory | 305904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974282325 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1974282325 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.3824124975 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 539433826 ps |
| CPU time | 33.66 seconds |
| Started | Sep 24 08:45:37 PM UTC 24 |
| Finished | Sep 24 08:46:12 PM UTC 24 |
| Peak memory | 233620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824124975 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3824124975 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.1615948699 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 7987562239 ps |
| CPU time | 223.72 seconds |
| Started | Sep 24 08:45:42 PM UTC 24 |
| Finished | Sep 24 08:49:30 PM UTC 24 |
| Peak memory | 345184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615948699 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1615948699 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.2299020628 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 41446230412 ps |
| CPU time | 259.66 seconds |
| Started | Sep 24 08:45:49 PM UTC 24 |
| Finished | Sep 24 08:50:13 PM UTC 24 |
| Peak memory | 463840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299020628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2299020628 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.1726089229 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 7158711103 ps |
| CPU time | 11.44 seconds |
| Started | Sep 24 08:46:13 PM UTC 24 |
| Finished | Sep 24 08:46:26 PM UTC 24 |
| Peak memory | 227356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726089229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1726089229 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.3343247635 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 53131380 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 08:46:23 PM UTC 24 |
| Finished | Sep 24 08:46:26 PM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343247635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3343247635 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.475149048 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 266062934163 ps |
| CPU time | 1452.66 seconds |
| Started | Sep 24 08:44:58 PM UTC 24 |
| Finished | Sep 24 09:09:29 PM UTC 24 |
| Peak memory | 1065780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475149048 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.475149048 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.330803883 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 5111639316 ps |
| CPU time | 92.41 seconds |
| Started | Sep 24 08:45:17 PM UTC 24 |
| Finished | Sep 24 08:46:51 PM UTC 24 |
| Peak memory | 287540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330803883 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.330803883 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.1603354895 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1499484964 ps |
| CPU time | 36.58 seconds |
| Started | Sep 24 08:44:57 PM UTC 24 |
| Finished | Sep 24 08:45:36 PM UTC 24 |
| Peak memory | 233644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603354895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1603354895 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.2076686291 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 213258186823 ps |
| CPU time | 2750.86 seconds |
| Started | Sep 24 08:46:25 PM UTC 24 |
| Finished | Sep 24 09:32:51 PM UTC 24 |
| Peak memory | 1526912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076686291 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.2076686291 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.2802246601 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 38216668 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:47:24 PM UTC 24 |
| Finished | Sep 24 08:47:26 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802246601 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2802246601 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.349189035 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1236104624 ps |
| CPU time | 4.78 seconds |
| Started | Sep 24 08:46:36 PM UTC 24 |
| Finished | Sep 24 08:46:42 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349189035 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.349189035 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.856525684 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 25165423473 ps |
| CPU time | 988.78 seconds |
| Started | Sep 24 08:46:34 PM UTC 24 |
| Finished | Sep 24 09:03:16 PM UTC 24 |
| Peak memory | 267052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856525684 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.856525684 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.2602953539 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 42090434830 ps |
| CPU time | 235.54 seconds |
| Started | Sep 24 08:46:43 PM UTC 24 |
| Finished | Sep 24 08:50:43 PM UTC 24 |
| Peak memory | 379768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602953539 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.2602953539 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.2088140410 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1366385831 ps |
| CPU time | 54.73 seconds |
| Started | Sep 24 08:46:52 PM UTC 24 |
| Finished | Sep 24 08:47:49 PM UTC 24 |
| Peak memory | 277172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088140410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.2088140410 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.898176017 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 595940015 ps |
| CPU time | 2.59 seconds |
| Started | Sep 24 08:47:01 PM UTC 24 |
| Finished | Sep 24 08:47:05 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898176017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.898176017 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.4154378796 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 75181485 ps |
| CPU time | 1.93 seconds |
| Started | Sep 24 08:47:05 PM UTC 24 |
| Finished | Sep 24 08:47:08 PM UTC 24 |
| Peak memory | 228372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154378796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.4154378796 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.2226642720 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 41948660308 ps |
| CPU time | 1275.37 seconds |
| Started | Sep 24 08:46:28 PM UTC 24 |
| Finished | Sep 24 09:08:00 PM UTC 24 |
| Peak memory | 1794836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226642720 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.2226642720 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.1286607062 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 16023075138 ps |
| CPU time | 227.12 seconds |
| Started | Sep 24 08:46:30 PM UTC 24 |
| Finished | Sep 24 08:50:21 PM UTC 24 |
| Peak memory | 412472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286607062 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1286607062 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.3334049926 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 79630594 ps |
| CPU time | 6.01 seconds |
| Started | Sep 24 08:46:28 PM UTC 24 |
| Finished | Sep 24 08:46:35 PM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334049926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3334049926 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.845820628 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 270225273128 ps |
| CPU time | 2601.27 seconds |
| Started | Sep 24 08:47:10 PM UTC 24 |
| Finished | Sep 24 09:31:04 PM UTC 24 |
| Peak memory | 1508084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845820628 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.845820628 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.850476106 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 40919911 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:48:41 PM UTC 24 |
| Finished | Sep 24 08:48:43 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850476106 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.850476106 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.3656951437 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 933738960 ps |
| CPU time | 25.67 seconds |
| Started | Sep 24 08:48:07 PM UTC 24 |
| Finished | Sep 24 08:48:34 PM UTC 24 |
| Peak memory | 240300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656951437 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3656951437 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.4013286284 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 7623952349 ps |
| CPU time | 329.03 seconds |
| Started | Sep 24 08:48:28 PM UTC 24 |
| Finished | Sep 24 08:54:02 PM UTC 24 |
| Peak memory | 340784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013286284 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.4013286284 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.3137269518 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 18181311856 ps |
| CPU time | 432 seconds |
| Started | Sep 24 08:48:30 PM UTC 24 |
| Finished | Sep 24 08:55:50 PM UTC 24 |
| Peak memory | 377588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137269518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3137269518 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.2882730756 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 530954295 ps |
| CPU time | 5.62 seconds |
| Started | Sep 24 08:48:34 PM UTC 24 |
| Finished | Sep 24 08:48:40 PM UTC 24 |
| Peak memory | 227164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882730756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2882730756 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.1089262669 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 154176576 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 08:48:35 PM UTC 24 |
| Finished | Sep 24 08:48:38 PM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089262669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1089262669 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.3165643783 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 51715833505 ps |
| CPU time | 1851.94 seconds |
| Started | Sep 24 08:47:38 PM UTC 24 |
| Finished | Sep 24 09:18:52 PM UTC 24 |
| Peak memory | 2423632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165643783 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.3165643783 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.1382326030 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 4485653402 ps |
| CPU time | 341.51 seconds |
| Started | Sep 24 08:47:50 PM UTC 24 |
| Finished | Sep 24 08:53:37 PM UTC 24 |
| Peak memory | 381880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382326030 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1382326030 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.4076112422 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 3500103970 ps |
| CPU time | 26.24 seconds |
| Started | Sep 24 08:47:27 PM UTC 24 |
| Finished | Sep 24 08:47:54 PM UTC 24 |
| Peak memory | 233712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076112422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.4076112422 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.1074934994 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 208694881251 ps |
| CPU time | 1472.46 seconds |
| Started | Sep 24 08:48:39 PM UTC 24 |
| Finished | Sep 24 09:13:30 PM UTC 24 |
| Peak memory | 1002524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074934994 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1074934994 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.4142217723 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 21943060 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:49:48 PM UTC 24 |
| Finished | Sep 24 08:49:50 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142217723 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.4142217723 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.1641184128 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 36477972568 ps |
| CPU time | 211.11 seconds |
| Started | Sep 24 08:49:25 PM UTC 24 |
| Finished | Sep 24 08:53:00 PM UTC 24 |
| Peak memory | 383772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641184128 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1641184128 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.617458864 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 78027708191 ps |
| CPU time | 778.33 seconds |
| Started | Sep 24 08:49:19 PM UTC 24 |
| Finished | Sep 24 09:02:28 PM UTC 24 |
| Peak memory | 256756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617458864 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.617458864 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.3963372442 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 5142151886 ps |
| CPU time | 86.37 seconds |
| Started | Sep 24 08:49:31 PM UTC 24 |
| Finished | Sep 24 08:50:59 PM UTC 24 |
| Peak memory | 258868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963372442 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3963372442 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.1316820896 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 27367193857 ps |
| CPU time | 457.31 seconds |
| Started | Sep 24 08:49:34 PM UTC 24 |
| Finished | Sep 24 08:57:17 PM UTC 24 |
| Peak memory | 613368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316820896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1316820896 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.65945589 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1344984318 ps |
| CPU time | 8.88 seconds |
| Started | Sep 24 08:49:37 PM UTC 24 |
| Finished | Sep 24 08:49:47 PM UTC 24 |
| Peak memory | 227208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65945589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.65945589 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.378635341 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 107615947 ps |
| CPU time | 2.08 seconds |
| Started | Sep 24 08:49:41 PM UTC 24 |
| Finished | Sep 24 08:49:44 PM UTC 24 |
| Peak memory | 227308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378635341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.378635341 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.4051509100 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 6805911418 ps |
| CPU time | 282.67 seconds |
| Started | Sep 24 08:48:50 PM UTC 24 |
| Finished | Sep 24 08:53:37 PM UTC 24 |
| Peak memory | 539756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051509100 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.4051509100 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.1102937332 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 52110033742 ps |
| CPU time | 282.06 seconds |
| Started | Sep 24 08:49:07 PM UTC 24 |
| Finished | Sep 24 08:53:54 PM UTC 24 |
| Peak memory | 447200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102937332 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1102937332 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.1464818512 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 5673257894 ps |
| CPU time | 71.95 seconds |
| Started | Sep 24 08:48:44 PM UTC 24 |
| Finished | Sep 24 08:49:58 PM UTC 24 |
| Peak memory | 234328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464818512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1464818512 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.41178708 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 210656420357 ps |
| CPU time | 1692.6 seconds |
| Started | Sep 24 08:49:45 PM UTC 24 |
| Finished | Sep 24 09:18:20 PM UTC 24 |
| Peak memory | 783152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41178708 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.41178708 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.456973521 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 42922937 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:51:00 PM UTC 24 |
| Finished | Sep 24 08:51:02 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456973521 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.456973521 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.3670990816 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 6316267337 ps |
| CPU time | 153.63 seconds |
| Started | Sep 24 08:50:23 PM UTC 24 |
| Finished | Sep 24 08:52:59 PM UTC 24 |
| Peak memory | 346860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670990816 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3670990816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.1929476704 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 136928383803 ps |
| CPU time | 1237.81 seconds |
| Started | Sep 24 08:50:14 PM UTC 24 |
| Finished | Sep 24 09:11:09 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929476704 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.1929476704 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.4026408704 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 12401626274 ps |
| CPU time | 114.87 seconds |
| Started | Sep 24 08:50:29 PM UTC 24 |
| Finished | Sep 24 08:52:26 PM UTC 24 |
| Peak memory | 324404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026408704 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.4026408704 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.868768972 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 438811831 ps |
| CPU time | 22.11 seconds |
| Started | Sep 24 08:50:44 PM UTC 24 |
| Finished | Sep 24 08:51:07 PM UTC 24 |
| Peak memory | 244392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868768972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.868768972 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.1763002285 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 15357800217 ps |
| CPU time | 13.27 seconds |
| Started | Sep 24 08:50:44 PM UTC 24 |
| Finished | Sep 24 08:50:58 PM UTC 24 |
| Peak memory | 227356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763002285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1763002285 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.2808182604 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 116189689 ps |
| CPU time | 1.9 seconds |
| Started | Sep 24 08:50:58 PM UTC 24 |
| Finished | Sep 24 08:51:01 PM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808182604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2808182604 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.3251007940 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1092694521 ps |
| CPU time | 41.71 seconds |
| Started | Sep 24 08:49:59 PM UTC 24 |
| Finished | Sep 24 08:50:43 PM UTC 24 |
| Peak memory | 238544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251007940 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.3251007940 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.706820533 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 52364163397 ps |
| CPU time | 543.18 seconds |
| Started | Sep 24 08:50:09 PM UTC 24 |
| Finished | Sep 24 08:59:20 PM UTC 24 |
| Peak memory | 574296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706820533 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.706820533 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.3871705990 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2157269616 ps |
| CPU time | 35.25 seconds |
| Started | Sep 24 08:49:51 PM UTC 24 |
| Finished | Sep 24 08:50:28 PM UTC 24 |
| Peak memory | 234068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871705990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3871705990 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.3786888183 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 22046062872 ps |
| CPU time | 2139.88 seconds |
| Started | Sep 24 08:50:59 PM UTC 24 |
| Finished | Sep 24 09:27:04 PM UTC 24 |
| Peak memory | 869168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786888183 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3786888183 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.3162996068 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 21891354 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:52:26 PM UTC 24 |
| Finished | Sep 24 08:52:29 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162996068 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3162996068 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.3184150073 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 86112199292 ps |
| CPU time | 488.22 seconds |
| Started | Sep 24 08:51:37 PM UTC 24 |
| Finished | Sep 24 08:59:53 PM UTC 24 |
| Peak memory | 578356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184150073 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.3184150073 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.4218713978 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 21013275790 ps |
| CPU time | 504.6 seconds |
| Started | Sep 24 08:51:23 PM UTC 24 |
| Finished | Sep 24 08:59:54 PM UTC 24 |
| Peak memory | 244576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218713978 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.4218713978 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.425775387 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 28884377080 ps |
| CPU time | 167.88 seconds |
| Started | Sep 24 08:51:49 PM UTC 24 |
| Finished | Sep 24 08:54:40 PM UTC 24 |
| Peak memory | 285804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425775387 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.425775387 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.4095647381 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3385881303 ps |
| CPU time | 93.62 seconds |
| Started | Sep 24 08:52:08 PM UTC 24 |
| Finished | Sep 24 08:53:44 PM UTC 24 |
| Peak memory | 299868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095647381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.4095647381 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.3186593312 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 651498488 ps |
| CPU time | 6.9 seconds |
| Started | Sep 24 08:52:09 PM UTC 24 |
| Finished | Sep 24 08:52:17 PM UTC 24 |
| Peak memory | 227204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186593312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3186593312 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.2734348066 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 87826386 ps |
| CPU time | 2.22 seconds |
| Started | Sep 24 08:52:18 PM UTC 24 |
| Finished | Sep 24 08:52:22 PM UTC 24 |
| Peak memory | 227700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734348066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2734348066 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.134316552 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1836745974351 ps |
| CPU time | 4162.32 seconds |
| Started | Sep 24 08:51:03 PM UTC 24 |
| Finished | Sep 24 10:01:17 PM UTC 24 |
| Peak memory | 3548000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134316552 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.134316552 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.320208078 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3790903996 ps |
| CPU time | 37.76 seconds |
| Started | Sep 24 08:51:08 PM UTC 24 |
| Finished | Sep 24 08:51:48 PM UTC 24 |
| Peak memory | 236316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320208078 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.320208078 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.883288013 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 906277799 ps |
| CPU time | 18.67 seconds |
| Started | Sep 24 08:51:02 PM UTC 24 |
| Finished | Sep 24 08:51:22 PM UTC 24 |
| Peak memory | 231632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883288013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.883288013 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.1498820083 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 87392049205 ps |
| CPU time | 854.66 seconds |
| Started | Sep 24 08:52:22 PM UTC 24 |
| Finished | Sep 24 09:06:49 PM UTC 24 |
| Peak memory | 683040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498820083 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1498820083 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.1452424028 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 31628181 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:53:38 PM UTC 24 |
| Finished | Sep 24 08:53:41 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452424028 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.1452424028 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.1985123892 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 18943472076 ps |
| CPU time | 347.09 seconds |
| Started | Sep 24 08:53:00 PM UTC 24 |
| Finished | Sep 24 08:58:52 PM UTC 24 |
| Peak memory | 418812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985123892 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1985123892 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.1541729500 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 4979567050 ps |
| CPU time | 464.52 seconds |
| Started | Sep 24 08:52:36 PM UTC 24 |
| Finished | Sep 24 09:00:27 PM UTC 24 |
| Peak memory | 244452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541729500 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.1541729500 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.3449528641 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 32180167087 ps |
| CPU time | 178.25 seconds |
| Started | Sep 24 08:53:01 PM UTC 24 |
| Finished | Sep 24 08:56:02 PM UTC 24 |
| Peak memory | 303968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449528641 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3449528641 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.1721959180 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 67966818989 ps |
| CPU time | 432.44 seconds |
| Started | Sep 24 08:53:01 PM UTC 24 |
| Finished | Sep 24 09:00:20 PM UTC 24 |
| Peak memory | 574260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721959180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1721959180 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.3538836022 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1472656847 ps |
| CPU time | 13.44 seconds |
| Started | Sep 24 08:53:07 PM UTC 24 |
| Finished | Sep 24 08:53:22 PM UTC 24 |
| Peak memory | 227168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538836022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3538836022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.1752491119 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 73041725 ps |
| CPU time | 2.01 seconds |
| Started | Sep 24 08:53:22 PM UTC 24 |
| Finished | Sep 24 08:53:26 PM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752491119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1752491119 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.1223998582 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 369526424361 ps |
| CPU time | 4255.85 seconds |
| Started | Sep 24 08:52:30 PM UTC 24 |
| Finished | Sep 24 10:04:13 PM UTC 24 |
| Peak memory | 4375376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223998582 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.1223998582 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.500225003 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 18615395923 ps |
| CPU time | 144.82 seconds |
| Started | Sep 24 08:52:35 PM UTC 24 |
| Finished | Sep 24 08:55:02 PM UTC 24 |
| Peak memory | 349240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500225003 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.500225003 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.1063567113 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 88865464 ps |
| CPU time | 4.03 seconds |
| Started | Sep 24 08:52:30 PM UTC 24 |
| Finished | Sep 24 08:52:35 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063567113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1063567113 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.1183902882 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3492118844 ps |
| CPU time | 73.58 seconds |
| Started | Sep 24 08:53:26 PM UTC 24 |
| Finished | Sep 24 08:54:42 PM UTC 24 |
| Peak memory | 294328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183902882 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1183902882 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.3059217217 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 37661774 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:54:56 PM UTC 24 |
| Finished | Sep 24 08:54:58 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059217217 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3059217217 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.991344160 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 8841892777 ps |
| CPU time | 76.87 seconds |
| Started | Sep 24 08:54:03 PM UTC 24 |
| Finished | Sep 24 08:55:22 PM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991344160 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.991344160 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.885911612 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 12087015478 ps |
| CPU time | 493.26 seconds |
| Started | Sep 24 08:53:55 PM UTC 24 |
| Finished | Sep 24 09:02:15 PM UTC 24 |
| Peak memory | 248944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885911612 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.885911612 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.4265575445 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 5726090854 ps |
| CPU time | 31.59 seconds |
| Started | Sep 24 08:54:17 PM UTC 24 |
| Finished | Sep 24 08:54:50 PM UTC 24 |
| Peak memory | 244536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265575445 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.4265575445 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.2458094077 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3359164081 ps |
| CPU time | 241.55 seconds |
| Started | Sep 24 08:54:41 PM UTC 24 |
| Finished | Sep 24 08:58:47 PM UTC 24 |
| Peak memory | 336608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458094077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.2458094077 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.1010707459 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 5482824892 ps |
| CPU time | 10.98 seconds |
| Started | Sep 24 08:54:43 PM UTC 24 |
| Finished | Sep 24 08:54:55 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010707459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1010707459 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.2755741721 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 133590979 ps |
| CPU time | 1.88 seconds |
| Started | Sep 24 08:54:52 PM UTC 24 |
| Finished | Sep 24 08:54:55 PM UTC 24 |
| Peak memory | 226360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755741721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2755741721 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.2038199738 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 32590568107 ps |
| CPU time | 2004.01 seconds |
| Started | Sep 24 08:53:42 PM UTC 24 |
| Finished | Sep 24 09:27:29 PM UTC 24 |
| Peak memory | 1387244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038199738 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.2038199738 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.3378458341 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 59788464365 ps |
| CPU time | 455 seconds |
| Started | Sep 24 08:53:45 PM UTC 24 |
| Finished | Sep 24 09:01:27 PM UTC 24 |
| Peak memory | 564080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378458341 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3378458341 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.1662476751 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 657412857 ps |
| CPU time | 36.34 seconds |
| Started | Sep 24 08:53:38 PM UTC 24 |
| Finished | Sep 24 08:54:16 PM UTC 24 |
| Peak memory | 231728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662476751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1662476751 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.4291628195 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 574539156 ps |
| CPU time | 26.84 seconds |
| Started | Sep 24 08:54:56 PM UTC 24 |
| Finished | Sep 24 08:55:24 PM UTC 24 |
| Peak memory | 233568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291628195 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.4291628195 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.1501082630 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 17775135 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:07:18 PM UTC 24 |
| Finished | Sep 24 08:07:21 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501082630 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1501082630 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.2718165438 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 10837007235 ps |
| CPU time | 310.51 seconds |
| Started | Sep 24 08:05:34 PM UTC 24 |
| Finished | Sep 24 08:10:49 PM UTC 24 |
| Peak memory | 473876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718165438 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2718165438 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.3067727612 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2646199637 ps |
| CPU time | 129.29 seconds |
| Started | Sep 24 08:05:40 PM UTC 24 |
| Finished | Sep 24 08:07:52 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067727612 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3067727612 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.3168002337 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3567615410 ps |
| CPU time | 73.05 seconds |
| Started | Sep 24 08:05:05 PM UTC 24 |
| Finished | Sep 24 08:06:20 PM UTC 24 |
| Peak memory | 234292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168002337 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3168002337 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.699185443 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 6411530448 ps |
| CPU time | 45.88 seconds |
| Started | Sep 24 08:06:30 PM UTC 24 |
| Finished | Sep 24 08:07:17 PM UTC 24 |
| Peak memory | 233968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699185443 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.699185443 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.3938235681 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2419118380 ps |
| CPU time | 48.74 seconds |
| Started | Sep 24 08:06:53 PM UTC 24 |
| Finished | Sep 24 08:07:43 PM UTC 24 |
| Peak memory | 244240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938235681 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3938235681 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.1938452055 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 7381055920 ps |
| CPU time | 78.32 seconds |
| Started | Sep 24 08:06:55 PM UTC 24 |
| Finished | Sep 24 08:08:15 PM UTC 24 |
| Peak memory | 234272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938452055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1938452055 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.401861221 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 11384916683 ps |
| CPU time | 254.54 seconds |
| Started | Sep 24 08:05:43 PM UTC 24 |
| Finished | Sep 24 08:10:02 PM UTC 24 |
| Peak memory | 431188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401861221 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.401861221 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.2801699654 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 36289761690 ps |
| CPU time | 351.49 seconds |
| Started | Sep 24 08:06:01 PM UTC 24 |
| Finished | Sep 24 08:11:57 PM UTC 24 |
| Peak memory | 480048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801699654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2801699654 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.517708842 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2812673005 ps |
| CPU time | 7.29 seconds |
| Started | Sep 24 08:06:21 PM UTC 24 |
| Finished | Sep 24 08:06:29 PM UTC 24 |
| Peak memory | 227300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517708842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.517708842 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.2370226192 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 153858514023 ps |
| CPU time | 3403.64 seconds |
| Started | Sep 24 08:05:03 PM UTC 24 |
| Finished | Sep 24 09:02:28 PM UTC 24 |
| Peak memory | 3832772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370226192 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.2370226192 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.109582978 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 21890857179 ps |
| CPU time | 357.54 seconds |
| Started | Sep 24 08:05:57 PM UTC 24 |
| Finished | Sep 24 08:12:00 PM UTC 24 |
| Peak memory | 361764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109582978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.109582978 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.3012396379 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1758689103 ps |
| CPU time | 36.77 seconds |
| Started | Sep 24 08:07:08 PM UTC 24 |
| Finished | Sep 24 08:07:46 PM UTC 24 |
| Peak memory | 276588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012396379 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3012396379 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.1248358723 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 77693595485 ps |
| CPU time | 258.47 seconds |
| Started | Sep 24 08:05:03 PM UTC 24 |
| Finished | Sep 24 08:09:26 PM UTC 24 |
| Peak memory | 402220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248358723 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1248358723 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.2524319476 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1096818161 ps |
| CPU time | 29.16 seconds |
| Started | Sep 24 08:05:03 PM UTC 24 |
| Finished | Sep 24 08:05:33 PM UTC 24 |
| Peak memory | 233676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524319476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2524319476 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.1490098394 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 12832322561 ps |
| CPU time | 113.96 seconds |
| Started | Sep 24 08:07:06 PM UTC 24 |
| Finished | Sep 24 08:09:02 PM UTC 24 |
| Peak memory | 283472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490098394 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1490098394 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all_with_rand_reset.4087756422 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9399269512 ps |
| CPU time | 37.06 seconds |
| Started | Sep 24 08:07:08 PM UTC 24 |
| Finished | Sep 24 08:07:46 PM UTC 24 |
| Peak memory | 260924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4087756422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_ with_rand_reset.4087756422 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.1073133808 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 339562766 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 08:05:29 PM UTC 24 |
| Finished | Sep 24 08:05:34 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073133808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.1073133808 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.1501359905 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 94489503 ps |
| CPU time | 3.8 seconds |
| Started | Sep 24 08:05:34 PM UTC 24 |
| Finished | Sep 24 08:05:39 PM UTC 24 |
| Peak memory | 229656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501359905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1501359905 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.753124397 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 65377985566 ps |
| CPU time | 2135.49 seconds |
| Started | Sep 24 08:05:08 PM UTC 24 |
| Finished | Sep 24 08:41:09 PM UTC 24 |
| Peak memory | 3101396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753124397 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.753124397 + enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.2353532152 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 93545378232 ps |
| CPU time | 2516.42 seconds |
| Started | Sep 24 08:05:10 PM UTC 24 |
| Finished | Sep 24 08:47:37 PM UTC 24 |
| Peak memory | 3070616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353532152 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2353532152 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.3448401038 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 190193991503 ps |
| CPU time | 1687.42 seconds |
| Started | Sep 24 08:05:14 PM UTC 24 |
| Finished | Sep 24 08:33:42 PM UTC 24 |
| Peak memory | 2316956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448401038 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3448401038 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.1666210338 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 30809686359 ps |
| CPU time | 1039.33 seconds |
| Started | Sep 24 08:05:28 PM UTC 24 |
| Finished | Sep 24 08:23:00 PM UTC 24 |
| Peak memory | 1698452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666210338 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.1666210338 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.109515321 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 388508864690 ps |
| CPU time | 3259.01 seconds |
| Started | Sep 24 08:05:28 PM UTC 24 |
| Finished | Sep 24 09:00:24 PM UTC 24 |
| Peak memory | 3668640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109515321 -assert nop ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.10951532 1 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2657202388 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1578792243 ps |
| CPU time | 111.75 seconds |
| Started | Sep 24 08:05:29 PM UTC 24 |
| Finished | Sep 24 08:07:23 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657202388 -assert no postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2657202 388 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.2695196390 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 27264233 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:57:03 PM UTC 24 |
| Finished | Sep 24 08:57:06 PM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695196390 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2695196390 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.2350340423 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 20460705700 ps |
| CPU time | 349.79 seconds |
| Started | Sep 24 08:55:25 PM UTC 24 |
| Finished | Sep 24 09:01:21 PM UTC 24 |
| Peak memory | 445408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350340423 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2350340423 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.3099650890 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 8648319923 ps |
| CPU time | 863.44 seconds |
| Started | Sep 24 08:55:23 PM UTC 24 |
| Finished | Sep 24 09:09:58 PM UTC 24 |
| Peak memory | 250680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099650890 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3099650890 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.3585091688 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 25246288531 ps |
| CPU time | 473.78 seconds |
| Started | Sep 24 08:55:43 PM UTC 24 |
| Finished | Sep 24 09:03:43 PM UTC 24 |
| Peak memory | 525108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585091688 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3585091688 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.504263432 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 5281460029 ps |
| CPU time | 245.56 seconds |
| Started | Sep 24 08:55:51 PM UTC 24 |
| Finished | Sep 24 09:00:00 PM UTC 24 |
| Peak memory | 332628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504263432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.504263432 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.72599393 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 449310980 ps |
| CPU time | 3.31 seconds |
| Started | Sep 24 08:56:04 PM UTC 24 |
| Finished | Sep 24 08:56:08 PM UTC 24 |
| Peak memory | 227164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72599393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.72599393 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.1131438314 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 37527226 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 08:56:09 PM UTC 24 |
| Finished | Sep 24 08:56:12 PM UTC 24 |
| Peak memory | 226360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131438314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1131438314 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.3012368724 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 448682180790 ps |
| CPU time | 4208.08 seconds |
| Started | Sep 24 08:55:03 PM UTC 24 |
| Finished | Sep 24 10:05:57 PM UTC 24 |
| Peak memory | 4332368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012368724 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.3012368724 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.3870333597 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 4543275243 ps |
| CPU time | 408.25 seconds |
| Started | Sep 24 08:55:17 PM UTC 24 |
| Finished | Sep 24 09:02:11 PM UTC 24 |
| Peak memory | 383988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870333597 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3870333597 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.3089671066 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 639758084 ps |
| CPU time | 16 seconds |
| Started | Sep 24 08:54:59 PM UTC 24 |
| Finished | Sep 24 08:55:16 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089671066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3089671066 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.292506014 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 148091343712 ps |
| CPU time | 2287.68 seconds |
| Started | Sep 24 08:56:13 PM UTC 24 |
| Finished | Sep 24 09:34:48 PM UTC 24 |
| Peak memory | 2790184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292506014 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.292506014 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.740843936 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 14542652 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:59:17 PM UTC 24 |
| Finished | Sep 24 08:59:19 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740843936 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.740843936 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.590476834 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 12267381318 ps |
| CPU time | 73.98 seconds |
| Started | Sep 24 08:57:57 PM UTC 24 |
| Finished | Sep 24 08:59:13 PM UTC 24 |
| Peak memory | 283672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590476834 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.590476834 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.717048809 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 7475780132 ps |
| CPU time | 172.38 seconds |
| Started | Sep 24 08:57:49 PM UTC 24 |
| Finished | Sep 24 09:00:44 PM UTC 24 |
| Peak memory | 234224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717048809 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.717048809 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.816745216 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 6447952903 ps |
| CPU time | 137.39 seconds |
| Started | Sep 24 08:58:43 PM UTC 24 |
| Finished | Sep 24 09:01:04 PM UTC 24 |
| Peak memory | 332588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816745216 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.816745216 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.1329832635 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 75309929477 ps |
| CPU time | 508.34 seconds |
| Started | Sep 24 08:58:48 PM UTC 24 |
| Finished | Sep 24 09:07:24 PM UTC 24 |
| Peak memory | 627440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329832635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1329832635 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.524134425 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1954480767 ps |
| CPU time | 20.48 seconds |
| Started | Sep 24 08:58:53 PM UTC 24 |
| Finished | Sep 24 08:59:15 PM UTC 24 |
| Peak memory | 227276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524134425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.524134425 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.40360360 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 56728710 ps |
| CPU time | 1.79 seconds |
| Started | Sep 24 08:59:14 PM UTC 24 |
| Finished | Sep 24 08:59:16 PM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40360360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.40360360 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.2723867597 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 684008480329 ps |
| CPU time | 3669.01 seconds |
| Started | Sep 24 08:57:19 PM UTC 24 |
| Finished | Sep 24 09:59:11 PM UTC 24 |
| Peak memory | 3728160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723867597 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.2723867597 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.362307198 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 9646958993 ps |
| CPU time | 303.06 seconds |
| Started | Sep 24 08:57:41 PM UTC 24 |
| Finished | Sep 24 09:02:49 PM UTC 24 |
| Peak memory | 330644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362307198 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.362307198 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.1255637153 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1256644381 ps |
| CPU time | 31.52 seconds |
| Started | Sep 24 08:57:06 PM UTC 24 |
| Finished | Sep 24 08:57:39 PM UTC 24 |
| Peak memory | 233684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255637153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1255637153 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.2133435856 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 12842545433 ps |
| CPU time | 998.53 seconds |
| Started | Sep 24 08:59:16 PM UTC 24 |
| Finished | Sep 24 09:16:07 PM UTC 24 |
| Peak memory | 552356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133435856 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2133435856 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.136053966 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 17050970 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 09:00:23 PM UTC 24 |
| Finished | Sep 24 09:00:25 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136053966 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.136053966 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.3650460662 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1984624727 ps |
| CPU time | 58.83 seconds |
| Started | Sep 24 08:59:55 PM UTC 24 |
| Finished | Sep 24 09:00:56 PM UTC 24 |
| Peak memory | 260780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650460662 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3650460662 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.2097036690 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 63762656980 ps |
| CPU time | 642.14 seconds |
| Started | Sep 24 08:59:53 PM UTC 24 |
| Finished | Sep 24 09:10:44 PM UTC 24 |
| Peak memory | 254776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097036690 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2097036690 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.1759441925 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 5054293420 ps |
| CPU time | 88.26 seconds |
| Started | Sep 24 09:00:01 PM UTC 24 |
| Finished | Sep 24 09:01:38 PM UTC 24 |
| Peak memory | 291892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759441925 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1759441925 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.3172998124 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 7916797935 ps |
| CPU time | 75.47 seconds |
| Started | Sep 24 09:00:09 PM UTC 24 |
| Finished | Sep 24 09:01:26 PM UTC 24 |
| Peak memory | 281392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172998124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3172998124 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.448334484 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2893795526 ps |
| CPU time | 7.81 seconds |
| Started | Sep 24 09:00:09 PM UTC 24 |
| Finished | Sep 24 09:00:18 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448334484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.448334484 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.3843989393 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 43715459 ps |
| CPU time | 2.48 seconds |
| Started | Sep 24 09:00:19 PM UTC 24 |
| Finished | Sep 24 09:00:22 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843989393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3843989393 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.3559519478 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 83854042463 ps |
| CPU time | 4118.37 seconds |
| Started | Sep 24 08:59:21 PM UTC 24 |
| Finished | Sep 24 10:08:48 PM UTC 24 |
| Peak memory | 4090768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559519478 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.3559519478 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.635956547 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1843141691 ps |
| CPU time | 14.52 seconds |
| Started | Sep 24 08:59:52 PM UTC 24 |
| Finished | Sep 24 09:00:08 PM UTC 24 |
| Peak memory | 234264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635956547 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.635956547 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.2972142098 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 864401838 ps |
| CPU time | 44.47 seconds |
| Started | Sep 24 08:59:20 PM UTC 24 |
| Finished | Sep 24 09:00:06 PM UTC 24 |
| Peak memory | 233644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972142098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.2972142098 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.3855905357 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 178367413151 ps |
| CPU time | 1189.33 seconds |
| Started | Sep 24 09:00:21 PM UTC 24 |
| Finished | Sep 24 09:20:26 PM UTC 24 |
| Peak memory | 1359004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855905357 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.3855905357 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.3031541851 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 18853491 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 09:01:31 PM UTC 24 |
| Finished | Sep 24 09:01:33 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031541851 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3031541851 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.190824196 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 32356521589 ps |
| CPU time | 313.14 seconds |
| Started | Sep 24 09:00:45 PM UTC 24 |
| Finished | Sep 24 09:06:03 PM UTC 24 |
| Peak memory | 531236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190824196 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.190824196 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.3632454325 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 20807384929 ps |
| CPU time | 100.36 seconds |
| Started | Sep 24 09:00:28 PM UTC 24 |
| Finished | Sep 24 09:02:11 PM UTC 24 |
| Peak memory | 234232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632454325 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3632454325 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.463787984 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 126377246724 ps |
| CPU time | 420.89 seconds |
| Started | Sep 24 09:00:53 PM UTC 24 |
| Finished | Sep 24 09:08:00 PM UTC 24 |
| Peak memory | 492564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463787984 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.463787984 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.3600999106 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2671367578 ps |
| CPU time | 127.32 seconds |
| Started | Sep 24 09:00:57 PM UTC 24 |
| Finished | Sep 24 09:03:07 PM UTC 24 |
| Peak memory | 279544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600999106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3600999106 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.2277340825 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 2225141771 ps |
| CPU time | 8.29 seconds |
| Started | Sep 24 09:01:05 PM UTC 24 |
| Finished | Sep 24 09:01:14 PM UTC 24 |
| Peak memory | 227356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277340825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2277340825 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.3631176448 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 79497303 ps |
| CPU time | 1.97 seconds |
| Started | Sep 24 09:01:15 PM UTC 24 |
| Finished | Sep 24 09:01:18 PM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631176448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3631176448 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.843804249 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 109035069702 ps |
| CPU time | 4092.49 seconds |
| Started | Sep 24 09:00:26 PM UTC 24 |
| Finished | Sep 24 10:09:24 PM UTC 24 |
| Peak memory | 4094868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843804249 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.843804249 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.2815599451 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 55660788420 ps |
| CPU time | 519.72 seconds |
| Started | Sep 24 09:00:26 PM UTC 24 |
| Finished | Sep 24 09:09:13 PM UTC 24 |
| Peak memory | 615148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815599451 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2815599451 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.3892904240 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 6043823142 ps |
| CPU time | 57.53 seconds |
| Started | Sep 24 09:00:25 PM UTC 24 |
| Finished | Sep 24 09:01:24 PM UTC 24 |
| Peak memory | 234264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892904240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3892904240 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.683806568 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 25441005353 ps |
| CPU time | 729.52 seconds |
| Started | Sep 24 09:01:19 PM UTC 24 |
| Finished | Sep 24 09:13:38 PM UTC 24 |
| Peak memory | 497020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683806568 -assert nopos tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.683806568 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.2626842172 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 38327613 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 09:02:18 PM UTC 24 |
| Finished | Sep 24 09:02:20 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626842172 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2626842172 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.1863789993 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 745022869 ps |
| CPU time | 45.95 seconds |
| Started | Sep 24 09:01:34 PM UTC 24 |
| Finished | Sep 24 09:02:22 PM UTC 24 |
| Peak memory | 244660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863789993 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1863789993 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.2497838690 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 22567370058 ps |
| CPU time | 650.95 seconds |
| Started | Sep 24 09:01:32 PM UTC 24 |
| Finished | Sep 24 09:12:32 PM UTC 24 |
| Peak memory | 246584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497838690 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.2497838690 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.2099873731 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 22111950798 ps |
| CPU time | 307.21 seconds |
| Started | Sep 24 09:01:39 PM UTC 24 |
| Finished | Sep 24 09:06:51 PM UTC 24 |
| Peak memory | 343036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099873731 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2099873731 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_error.3463249651 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 778676013 ps |
| CPU time | 42.92 seconds |
| Started | Sep 24 09:01:43 PM UTC 24 |
| Finished | Sep 24 09:02:28 PM UTC 24 |
| Peak memory | 250488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463249651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.3463249651 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.2171283553 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 4508777211 ps |
| CPU time | 10.18 seconds |
| Started | Sep 24 09:02:12 PM UTC 24 |
| Finished | Sep 24 09:02:24 PM UTC 24 |
| Peak memory | 227296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171283553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2171283553 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.635369788 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 133489160 ps |
| CPU time | 2.55 seconds |
| Started | Sep 24 09:02:13 PM UTC 24 |
| Finished | Sep 24 09:02:16 PM UTC 24 |
| Peak memory | 229480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635369788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.635369788 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.2686759019 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 127285866616 ps |
| CPU time | 2636.25 seconds |
| Started | Sep 24 09:01:32 PM UTC 24 |
| Finished | Sep 24 09:45:58 PM UTC 24 |
| Peak memory | 3066664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686759019 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.2686759019 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.3724442425 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 4139886884 ps |
| CPU time | 317.28 seconds |
| Started | Sep 24 09:01:32 PM UTC 24 |
| Finished | Sep 24 09:06:54 PM UTC 24 |
| Peak memory | 375904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724442425 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3724442425 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.1998969526 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1727899152 ps |
| CPU time | 9.18 seconds |
| Started | Sep 24 09:01:32 PM UTC 24 |
| Finished | Sep 24 09:01:42 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998969526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1998969526 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.1005606934 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 76291617455 ps |
| CPU time | 1417.86 seconds |
| Started | Sep 24 09:02:16 PM UTC 24 |
| Finished | Sep 24 09:26:11 PM UTC 24 |
| Peak memory | 713784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005606934 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1005606934 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.1258085004 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 15937370 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 09:02:50 PM UTC 24 |
| Finished | Sep 24 09:02:52 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258085004 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1258085004 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.577322658 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 34521731726 ps |
| CPU time | 262.61 seconds |
| Started | Sep 24 09:02:28 PM UTC 24 |
| Finished | Sep 24 09:06:55 PM UTC 24 |
| Peak memory | 388248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577322658 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.577322658 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.3034244168 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 11682310717 ps |
| CPU time | 333.79 seconds |
| Started | Sep 24 09:02:27 PM UTC 24 |
| Finished | Sep 24 09:08:07 PM UTC 24 |
| Peak memory | 240436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034244168 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.3034244168 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.501634945 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 16712745208 ps |
| CPU time | 114.78 seconds |
| Started | Sep 24 09:02:28 PM UTC 24 |
| Finished | Sep 24 09:04:26 PM UTC 24 |
| Peak memory | 309932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501634945 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.501634945 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.1166098327 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 89868272307 ps |
| CPU time | 141.5 seconds |
| Started | Sep 24 09:02:28 PM UTC 24 |
| Finished | Sep 24 09:04:52 PM UTC 24 |
| Peak memory | 347060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166098327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1166098327 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.388680786 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2122473462 ps |
| CPU time | 9.41 seconds |
| Started | Sep 24 09:02:36 PM UTC 24 |
| Finished | Sep 24 09:02:46 PM UTC 24 |
| Peak memory | 227272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388680786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.388680786 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.3740674951 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 249520000 ps |
| CPU time | 2.31 seconds |
| Started | Sep 24 09:02:47 PM UTC 24 |
| Finished | Sep 24 09:02:50 PM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740674951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3740674951 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.1112452575 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 44747197978 ps |
| CPU time | 1013.3 seconds |
| Started | Sep 24 09:02:23 PM UTC 24 |
| Finished | Sep 24 09:19:29 PM UTC 24 |
| Peak memory | 846668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112452575 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.1112452575 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.1921146009 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 12134721824 ps |
| CPU time | 364.51 seconds |
| Started | Sep 24 09:02:25 PM UTC 24 |
| Finished | Sep 24 09:08:35 PM UTC 24 |
| Peak memory | 506704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921146009 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.1921146009 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.3486317015 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2153673288 ps |
| CPU time | 12.51 seconds |
| Started | Sep 24 09:02:21 PM UTC 24 |
| Finished | Sep 24 09:02:34 PM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486317015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3486317015 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.1308305681 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 9399490909 ps |
| CPU time | 221.31 seconds |
| Started | Sep 24 09:02:50 PM UTC 24 |
| Finished | Sep 24 09:06:35 PM UTC 24 |
| Peak memory | 361888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308305681 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1308305681 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.3813576767 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 16850705 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 09:04:57 PM UTC 24 |
| Finished | Sep 24 09:04:59 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813576767 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3813576767 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.1017503691 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 6626417798 ps |
| CPU time | 119.24 seconds |
| Started | Sep 24 09:03:42 PM UTC 24 |
| Finished | Sep 24 09:05:44 PM UTC 24 |
| Peak memory | 269020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017503691 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1017503691 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.1500022522 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 104829487417 ps |
| CPU time | 831.7 seconds |
| Started | Sep 24 09:03:17 PM UTC 24 |
| Finished | Sep 24 09:17:20 PM UTC 24 |
| Peak memory | 260916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500022522 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1500022522 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.1657336437 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 7248644379 ps |
| CPU time | 151.55 seconds |
| Started | Sep 24 09:03:43 PM UTC 24 |
| Finished | Sep 24 09:06:18 PM UTC 24 |
| Peak memory | 373892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657336437 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1657336437 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.3794396685 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 117285790106 ps |
| CPU time | 424.23 seconds |
| Started | Sep 24 09:04:27 PM UTC 24 |
| Finished | Sep 24 09:11:37 PM UTC 24 |
| Peak memory | 590900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794396685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3794396685 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.2406337397 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 7400281618 ps |
| CPU time | 18.84 seconds |
| Started | Sep 24 09:04:34 PM UTC 24 |
| Finished | Sep 24 09:04:54 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406337397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2406337397 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.1734343751 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 46103784 ps |
| CPU time | 2.05 seconds |
| Started | Sep 24 09:04:53 PM UTC 24 |
| Finished | Sep 24 09:04:56 PM UTC 24 |
| Peak memory | 227364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734343751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1734343751 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.714994164 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 47535219964 ps |
| CPU time | 2488.51 seconds |
| Started | Sep 24 09:02:53 PM UTC 24 |
| Finished | Sep 24 09:44:51 PM UTC 24 |
| Peak memory | 1682232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714994164 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.714994164 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.3445498333 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2486251913 ps |
| CPU time | 114.6 seconds |
| Started | Sep 24 09:03:07 PM UTC 24 |
| Finished | Sep 24 09:05:04 PM UTC 24 |
| Peak memory | 271412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445498333 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3445498333 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.1291923106 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2692918662 ps |
| CPU time | 48.56 seconds |
| Started | Sep 24 09:02:51 PM UTC 24 |
| Finished | Sep 24 09:03:41 PM UTC 24 |
| Peak memory | 233712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291923106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1291923106 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.4118628878 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 27323796485 ps |
| CPU time | 879.21 seconds |
| Started | Sep 24 09:04:55 PM UTC 24 |
| Finished | Sep 24 09:19:46 PM UTC 24 |
| Peak memory | 1098536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118628878 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.4118628878 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.3861203816 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 33318413 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 09:06:49 PM UTC 24 |
| Finished | Sep 24 09:06:52 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861203816 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3861203816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.3775381822 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 32828183390 ps |
| CPU time | 275.52 seconds |
| Started | Sep 24 09:05:45 PM UTC 24 |
| Finished | Sep 24 09:10:24 PM UTC 24 |
| Peak memory | 431152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775381822 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3775381822 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.3777083716 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 78951820590 ps |
| CPU time | 624.87 seconds |
| Started | Sep 24 09:05:33 PM UTC 24 |
| Finished | Sep 24 09:16:06 PM UTC 24 |
| Peak memory | 254716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777083716 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3777083716 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1995134569 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 5511826820 ps |
| CPU time | 123.26 seconds |
| Started | Sep 24 09:06:04 PM UTC 24 |
| Finished | Sep 24 09:08:09 PM UTC 24 |
| Peak memory | 328760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995134569 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1995134569 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.715019121 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 64380158801 ps |
| CPU time | 438.85 seconds |
| Started | Sep 24 09:06:19 PM UTC 24 |
| Finished | Sep 24 09:13:44 PM UTC 24 |
| Peak memory | 551924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715019121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.715019121 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.2304203410 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 805749899 ps |
| CPU time | 4.25 seconds |
| Started | Sep 24 09:06:35 PM UTC 24 |
| Finished | Sep 24 09:06:40 PM UTC 24 |
| Peak memory | 227204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304203410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2304203410 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.685253190 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 170033259 ps |
| CPU time | 2.01 seconds |
| Started | Sep 24 09:06:41 PM UTC 24 |
| Finished | Sep 24 09:06:44 PM UTC 24 |
| Peak memory | 226364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685253190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.685253190 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.1104553887 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 215101577646 ps |
| CPU time | 2224.02 seconds |
| Started | Sep 24 09:05:05 PM UTC 24 |
| Finished | Sep 24 09:42:36 PM UTC 24 |
| Peak memory | 1438448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104553887 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.1104553887 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.2585998927 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 6596000252 ps |
| CPU time | 126.99 seconds |
| Started | Sep 24 09:05:32 PM UTC 24 |
| Finished | Sep 24 09:07:42 PM UTC 24 |
| Peak memory | 312236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585998927 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2585998927 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.2943444196 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2490638885 ps |
| CPU time | 30.33 seconds |
| Started | Sep 24 09:05:00 PM UTC 24 |
| Finished | Sep 24 09:05:32 PM UTC 24 |
| Peak memory | 233712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943444196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2943444196 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.1119957776 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 29055012424 ps |
| CPU time | 757.22 seconds |
| Started | Sep 24 09:06:45 PM UTC 24 |
| Finished | Sep 24 09:19:32 PM UTC 24 |
| Peak memory | 339000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119957776 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1119957776 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.4068830127 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 20186155 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 09:08:07 PM UTC 24 |
| Finished | Sep 24 09:08:10 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068830127 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.4068830127 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.1702567561 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 4193975014 ps |
| CPU time | 85.95 seconds |
| Started | Sep 24 09:07:07 PM UTC 24 |
| Finished | Sep 24 09:08:35 PM UTC 24 |
| Peak memory | 281436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702567561 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1702567561 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.1345859959 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 6773897444 ps |
| CPU time | 634.5 seconds |
| Started | Sep 24 09:06:56 PM UTC 24 |
| Finished | Sep 24 09:17:38 PM UTC 24 |
| Peak memory | 250616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345859959 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.1345859959 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.3636442950 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 15725109047 ps |
| CPU time | 299.22 seconds |
| Started | Sep 24 09:07:25 PM UTC 24 |
| Finished | Sep 24 09:12:29 PM UTC 24 |
| Peak memory | 435060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636442950 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3636442950 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.3760581947 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 15367048522 ps |
| CPU time | 223.9 seconds |
| Started | Sep 24 09:07:43 PM UTC 24 |
| Finished | Sep 24 09:11:31 PM UTC 24 |
| Peak memory | 398132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760581947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3760581947 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.1144232568 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 630241339 ps |
| CPU time | 6.48 seconds |
| Started | Sep 24 09:08:01 PM UTC 24 |
| Finished | Sep 24 09:08:09 PM UTC 24 |
| Peak memory | 227264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144232568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1144232568 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.3140650128 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 85416056 ps |
| CPU time | 2.12 seconds |
| Started | Sep 24 09:08:01 PM UTC 24 |
| Finished | Sep 24 09:08:04 PM UTC 24 |
| Peak memory | 227300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140650128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3140650128 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.3981931481 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 69009008831 ps |
| CPU time | 3082.59 seconds |
| Started | Sep 24 09:06:52 PM UTC 24 |
| Finished | Sep 24 09:58:52 PM UTC 24 |
| Peak memory | 3423012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981931481 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.3981931481 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.2691483938 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 9981424426 ps |
| CPU time | 302.28 seconds |
| Started | Sep 24 09:06:55 PM UTC 24 |
| Finished | Sep 24 09:12:01 PM UTC 24 |
| Peak memory | 504620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691483938 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2691483938 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.474870342 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 209386504 ps |
| CPU time | 12.88 seconds |
| Started | Sep 24 09:06:51 PM UTC 24 |
| Finished | Sep 24 09:07:06 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474870342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.474870342 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.1808896145 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 21958927445 ps |
| CPU time | 305.56 seconds |
| Started | Sep 24 09:08:05 PM UTC 24 |
| Finished | Sep 24 09:13:16 PM UTC 24 |
| Peak memory | 344812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808896145 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1808896145 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.575348788 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 25312814 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 09:09:15 PM UTC 24 |
| Finished | Sep 24 09:09:17 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575348788 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.575348788 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.3839375975 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1563647178 ps |
| CPU time | 10.14 seconds |
| Started | Sep 24 09:08:36 PM UTC 24 |
| Finished | Sep 24 09:08:47 PM UTC 24 |
| Peak memory | 244700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839375975 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3839375975 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.1323616467 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 61202848826 ps |
| CPU time | 418.69 seconds |
| Started | Sep 24 09:08:14 PM UTC 24 |
| Finished | Sep 24 09:15:18 PM UTC 24 |
| Peak memory | 244536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323616467 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.1323616467 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.3836956851 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 22006869209 ps |
| CPU time | 153.58 seconds |
| Started | Sep 24 09:08:36 PM UTC 24 |
| Finished | Sep 24 09:11:12 PM UTC 24 |
| Peak memory | 283440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836956851 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3836956851 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.3205087985 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 20620232072 ps |
| CPU time | 158.05 seconds |
| Started | Sep 24 09:08:48 PM UTC 24 |
| Finished | Sep 24 09:11:29 PM UTC 24 |
| Peak memory | 363572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205087985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3205087985 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.546530911 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2728985376 ps |
| CPU time | 7.38 seconds |
| Started | Sep 24 09:09:08 PM UTC 24 |
| Finished | Sep 24 09:09:17 PM UTC 24 |
| Peak memory | 227304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546530911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.546530911 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.189156785 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 45390445 ps |
| CPU time | 2.77 seconds |
| Started | Sep 24 09:09:09 PM UTC 24 |
| Finished | Sep 24 09:09:13 PM UTC 24 |
| Peak memory | 227404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189156785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.189156785 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.1837375847 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 92776796739 ps |
| CPU time | 1728.61 seconds |
| Started | Sep 24 09:08:11 PM UTC 24 |
| Finished | Sep 24 09:37:21 PM UTC 24 |
| Peak memory | 2331468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837375847 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.1837375847 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.3903681867 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1266551276 ps |
| CPU time | 63.92 seconds |
| Started | Sep 24 09:08:11 PM UTC 24 |
| Finished | Sep 24 09:09:16 PM UTC 24 |
| Peak memory | 246492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903681867 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.3903681867 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.2400251006 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 196282540 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 09:08:10 PM UTC 24 |
| Finished | Sep 24 09:08:13 PM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400251006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2400251006 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.2375155384 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 52314913682 ps |
| CPU time | 774.64 seconds |
| Started | Sep 24 09:09:15 PM UTC 24 |
| Finished | Sep 24 09:22:20 PM UTC 24 |
| Peak memory | 539960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375155384 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2375155384 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.4201208370 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 49730318 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:08:17 PM UTC 24 |
| Finished | Sep 24 08:08:19 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201208370 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.4201208370 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.1805152995 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 18782747897 ps |
| CPU time | 133.46 seconds |
| Started | Sep 24 08:07:36 PM UTC 24 |
| Finished | Sep 24 08:09:52 PM UTC 24 |
| Peak memory | 316124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805152995 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1805152995 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.3428006202 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 10874486471 ps |
| CPU time | 275.7 seconds |
| Started | Sep 24 08:07:36 PM UTC 24 |
| Finished | Sep 24 08:12:16 PM UTC 24 |
| Peak memory | 400476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428006202 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3428006202 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.3675713871 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 29499502756 ps |
| CPU time | 264.46 seconds |
| Started | Sep 24 08:07:24 PM UTC 24 |
| Finished | Sep 24 08:11:52 PM UTC 24 |
| Peak memory | 240412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675713871 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3675713871 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.2795782234 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2846297769 ps |
| CPU time | 43.52 seconds |
| Started | Sep 24 08:07:54 PM UTC 24 |
| Finished | Sep 24 08:08:39 PM UTC 24 |
| Peak memory | 234224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795782234 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2795782234 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.2041136565 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2956959816 ps |
| CPU time | 27.26 seconds |
| Started | Sep 24 08:07:57 PM UTC 24 |
| Finished | Sep 24 08:08:26 PM UTC 24 |
| Peak memory | 234256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041136565 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2041136565 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.733508520 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3786353391 ps |
| CPU time | 56.11 seconds |
| Started | Sep 24 08:08:10 PM UTC 24 |
| Finished | Sep 24 08:09:08 PM UTC 24 |
| Peak memory | 234332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733508520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_u nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.733508520 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.2241172592 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 520960153 ps |
| CPU time | 11.1 seconds |
| Started | Sep 24 08:07:44 PM UTC 24 |
| Finished | Sep 24 08:07:56 PM UTC 24 |
| Peak memory | 234164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241172592 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2241172592 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.200793526 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 6222412107 ps |
| CPU time | 101.86 seconds |
| Started | Sep 24 08:07:48 PM UTC 24 |
| Finished | Sep 24 08:09:32 PM UTC 24 |
| Peak memory | 316500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200793526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.200793526 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.2330085448 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 5428976853 ps |
| CPU time | 15.06 seconds |
| Started | Sep 24 08:07:53 PM UTC 24 |
| Finished | Sep 24 08:08:09 PM UTC 24 |
| Peak memory | 227360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330085448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2330085448 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.3809261722 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 92669202 ps |
| CPU time | 1.75 seconds |
| Started | Sep 24 08:08:13 PM UTC 24 |
| Finished | Sep 24 08:08:16 PM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809261722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3809261722 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.1685621352 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 22925305064 ps |
| CPU time | 2502.34 seconds |
| Started | Sep 24 08:07:21 PM UTC 24 |
| Finished | Sep 24 08:49:33 PM UTC 24 |
| Peak memory | 1592312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685621352 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.1685621352 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.794651272 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 5858022718 ps |
| CPU time | 181.66 seconds |
| Started | Sep 24 08:07:47 PM UTC 24 |
| Finished | Sep 24 08:10:52 PM UTC 24 |
| Peak memory | 374080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794651272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.794651272 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.946626388 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2388146900 ps |
| CPU time | 50.47 seconds |
| Started | Sep 24 08:07:23 PM UTC 24 |
| Finished | Sep 24 08:08:16 PM UTC 24 |
| Peak memory | 244504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946626388 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.946626388 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.26412610 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 509345115 ps |
| CPU time | 31.92 seconds |
| Started | Sep 24 08:07:19 PM UTC 24 |
| Finished | Sep 24 08:07:53 PM UTC 24 |
| Peak memory | 231852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26412610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.26412610 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.2830564353 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 279749095610 ps |
| CPU time | 1904.16 seconds |
| Started | Sep 24 08:08:17 PM UTC 24 |
| Finished | Sep 24 08:40:24 PM UTC 24 |
| Peak memory | 1807516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830564353 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2830564353 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.3655151266 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2282557688 ps |
| CPU time | 187.8 seconds |
| Started | Sep 24 08:08:17 PM UTC 24 |
| Finished | Sep 24 08:11:27 PM UTC 24 |
| Peak memory | 283644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3655151266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_ with_rand_reset.3655151266 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.3039060736 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 64721967 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:10:03 PM UTC 24 |
| Finished | Sep 24 08:10:05 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039060736 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3039060736 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.4196991703 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 26535631333 ps |
| CPU time | 313.97 seconds |
| Started | Sep 24 08:08:40 PM UTC 24 |
| Finished | Sep 24 08:13:59 PM UTC 24 |
| Peak memory | 447280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196991703 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4196991703 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.1932545596 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 9178442532 ps |
| CPU time | 46.3 seconds |
| Started | Sep 24 08:08:51 PM UTC 24 |
| Finished | Sep 24 08:09:39 PM UTC 24 |
| Peak memory | 236344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932545596 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1932545596 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.1562106774 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 10446940970 ps |
| CPU time | 335.82 seconds |
| Started | Sep 24 08:08:35 PM UTC 24 |
| Finished | Sep 24 08:14:16 PM UTC 24 |
| Peak memory | 242428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562106774 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.1562106774 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.711718773 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 7457574711 ps |
| CPU time | 45.42 seconds |
| Started | Sep 24 08:09:35 PM UTC 24 |
| Finished | Sep 24 08:10:22 PM UTC 24 |
| Peak memory | 244464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711718773 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.711718773 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.4066601895 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1102420086 ps |
| CPU time | 24.77 seconds |
| Started | Sep 24 08:09:40 PM UTC 24 |
| Finished | Sep 24 08:10:06 PM UTC 24 |
| Peak memory | 233892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066601895 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.4066601895 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.4219091130 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2466790431 ps |
| CPU time | 37.82 seconds |
| Started | Sep 24 08:09:41 PM UTC 24 |
| Finished | Sep 24 08:10:20 PM UTC 24 |
| Peak memory | 234024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219091130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.4219091130 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.4028306817 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 11269567474 ps |
| CPU time | 69.93 seconds |
| Started | Sep 24 08:09:03 PM UTC 24 |
| Finished | Sep 24 08:10:15 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028306817 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.4028306817 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.4285709600 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9389452116 ps |
| CPU time | 404.58 seconds |
| Started | Sep 24 08:09:27 PM UTC 24 |
| Finished | Sep 24 08:16:17 PM UTC 24 |
| Peak memory | 383984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285709600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.4285709600 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.2461694571 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 5168446447 ps |
| CPU time | 12.9 seconds |
| Started | Sep 24 08:09:33 PM UTC 24 |
| Finished | Sep 24 08:09:47 PM UTC 24 |
| Peak memory | 227300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461694571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2461694571 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.308283006 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 163213154 ps |
| CPU time | 2.32 seconds |
| Started | Sep 24 08:09:48 PM UTC 24 |
| Finished | Sep 24 08:09:51 PM UTC 24 |
| Peak memory | 227300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308283006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmaske d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.308283006 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.553715062 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 37662849518 ps |
| CPU time | 1127.83 seconds |
| Started | Sep 24 08:08:25 PM UTC 24 |
| Finished | Sep 24 08:27:27 PM UTC 24 |
| Peak memory | 1557340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553715062 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.553715062 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.145171652 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2377552347 ps |
| CPU time | 61.74 seconds |
| Started | Sep 24 08:09:09 PM UTC 24 |
| Finished | Sep 24 08:10:13 PM UTC 24 |
| Peak memory | 263284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145171652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.145171652 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.3467140566 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 7673315936 ps |
| CPU time | 251.62 seconds |
| Started | Sep 24 08:08:27 PM UTC 24 |
| Finished | Sep 24 08:12:42 PM UTC 24 |
| Peak memory | 422748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467140566 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3467140566 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.1446072666 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2997103489 ps |
| CPU time | 72.28 seconds |
| Started | Sep 24 08:08:20 PM UTC 24 |
| Finished | Sep 24 08:09:34 PM UTC 24 |
| Peak memory | 234284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446072666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1446072666 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.2538320937 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 19984353653 ps |
| CPU time | 2002.61 seconds |
| Started | Sep 24 08:09:52 PM UTC 24 |
| Finished | Sep 24 08:43:42 PM UTC 24 |
| Peak memory | 675156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538320937 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2538320937 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.836872597 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 16580635 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:11:28 PM UTC 24 |
| Finished | Sep 24 08:11:30 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836872597 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.836872597 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.4013846248 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 15962692302 ps |
| CPU time | 379.7 seconds |
| Started | Sep 24 08:10:26 PM UTC 24 |
| Finished | Sep 24 08:16:51 PM UTC 24 |
| Peak memory | 551852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013846248 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.4013846248 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.885775282 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 10313977653 ps |
| CPU time | 321.66 seconds |
| Started | Sep 24 08:10:26 PM UTC 24 |
| Finished | Sep 24 08:15:53 PM UTC 24 |
| Peak memory | 334556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885775282 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.885775282 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.3574495148 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 4821569234 ps |
| CPU time | 51.66 seconds |
| Started | Sep 24 08:10:16 PM UTC 24 |
| Finished | Sep 24 08:11:10 PM UTC 24 |
| Peak memory | 234552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574495148 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3574495148 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.3748270191 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1483960192 ps |
| CPU time | 23.9 seconds |
| Started | Sep 24 08:10:53 PM UTC 24 |
| Finished | Sep 24 08:11:19 PM UTC 24 |
| Peak memory | 233380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748270191 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.3748270191 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.294485151 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 401632644 ps |
| CPU time | 42.38 seconds |
| Started | Sep 24 08:10:56 PM UTC 24 |
| Finished | Sep 24 08:11:40 PM UTC 24 |
| Peak memory | 233840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294485151 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.294485151 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.1164546183 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 10704854545 ps |
| CPU time | 69.41 seconds |
| Started | Sep 24 08:11:11 PM UTC 24 |
| Finished | Sep 24 08:12:22 PM UTC 24 |
| Peak memory | 234496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164546183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1164546183 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.3453716312 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4945234567 ps |
| CPU time | 131.47 seconds |
| Started | Sep 24 08:10:27 PM UTC 24 |
| Finished | Sep 24 08:12:41 PM UTC 24 |
| Peak memory | 308320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453716312 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3453716312 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.3205169042 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 36441317242 ps |
| CPU time | 239.22 seconds |
| Started | Sep 24 08:10:45 PM UTC 24 |
| Finished | Sep 24 08:14:48 PM UTC 24 |
| Peak memory | 437080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205169042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3205169042 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.1251814162 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1862322335 ps |
| CPU time | 4.7 seconds |
| Started | Sep 24 08:10:50 PM UTC 24 |
| Finished | Sep 24 08:10:56 PM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251814162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1251814162 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.3076222367 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 47981216 ps |
| CPU time | 2.05 seconds |
| Started | Sep 24 08:11:14 PM UTC 24 |
| Finished | Sep 24 08:11:17 PM UTC 24 |
| Peak memory | 227300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076222367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3076222367 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.908089147 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 23847664880 ps |
| CPU time | 195.62 seconds |
| Started | Sep 24 08:10:07 PM UTC 24 |
| Finished | Sep 24 08:13:26 PM UTC 24 |
| Peak memory | 346972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908089147 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.908089147 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.2623022020 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 121254292887 ps |
| CPU time | 518.48 seconds |
| Started | Sep 24 08:10:27 PM UTC 24 |
| Finished | Sep 24 08:19:13 PM UTC 24 |
| Peak memory | 547996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623022020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2623022020 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.3886080393 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 664360990 ps |
| CPU time | 36.68 seconds |
| Started | Sep 24 08:10:06 PM UTC 24 |
| Finished | Sep 24 08:10:44 PM UTC 24 |
| Peak memory | 231524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886080393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3886080393 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.2354163415 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 36890496828 ps |
| CPU time | 1101.77 seconds |
| Started | Sep 24 08:11:18 PM UTC 24 |
| Finished | Sep 24 08:29:54 PM UTC 24 |
| Peak memory | 363940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354163415 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2354163415 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.3241921591 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 61173701 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:12:42 PM UTC 24 |
| Finished | Sep 24 08:12:44 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241921591 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3241921591 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.358172057 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 6252938042 ps |
| CPU time | 195.96 seconds |
| Started | Sep 24 08:11:53 PM UTC 24 |
| Finished | Sep 24 08:15:12 PM UTC 24 |
| Peak memory | 357076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358172057 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.358172057 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.2210402255 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 21392569262 ps |
| CPU time | 318.77 seconds |
| Started | Sep 24 08:11:58 PM UTC 24 |
| Finished | Sep 24 08:17:22 PM UTC 24 |
| Peak memory | 332564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210402255 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.2210402255 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.3176033529 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 10308909828 ps |
| CPU time | 544.22 seconds |
| Started | Sep 24 08:11:52 PM UTC 24 |
| Finished | Sep 24 08:21:03 PM UTC 24 |
| Peak memory | 244536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176033529 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3176033529 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.3908378435 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 3137887022 ps |
| CPU time | 24.78 seconds |
| Started | Sep 24 08:12:23 PM UTC 24 |
| Finished | Sep 24 08:12:49 PM UTC 24 |
| Peak memory | 234068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908378435 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3908378435 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.1601338226 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 235253452 ps |
| CPU time | 11.27 seconds |
| Started | Sep 24 08:12:26 PM UTC 24 |
| Finished | Sep 24 08:12:38 PM UTC 24 |
| Peak memory | 231368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601338226 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1601338226 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.1805008310 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 4052450212 ps |
| CPU time | 58.39 seconds |
| Started | Sep 24 08:12:31 PM UTC 24 |
| Finished | Sep 24 08:13:31 PM UTC 24 |
| Peak memory | 234276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805008310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1805008310 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.3092320342 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 8272226608 ps |
| CPU time | 38.54 seconds |
| Started | Sep 24 08:12:00 PM UTC 24 |
| Finished | Sep 24 08:12:41 PM UTC 24 |
| Peak memory | 248600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092320342 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3092320342 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.448130374 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 12345314761 ps |
| CPU time | 18.23 seconds |
| Started | Sep 24 08:12:23 PM UTC 24 |
| Finished | Sep 24 08:12:42 PM UTC 24 |
| Peak memory | 227656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448130374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.448130374 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.3804469859 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 88422937 ps |
| CPU time | 2.23 seconds |
| Started | Sep 24 08:12:41 PM UTC 24 |
| Finished | Sep 24 08:12:44 PM UTC 24 |
| Peak memory | 227404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804469859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3804469859 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.1306402709 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 467817664597 ps |
| CPU time | 3147.63 seconds |
| Started | Sep 24 08:11:31 PM UTC 24 |
| Finished | Sep 24 09:04:32 PM UTC 24 |
| Peak memory | 3519328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306402709 -assert nopostproc +UVM _TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.1306402709 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.2623314997 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 5223288290 ps |
| CPU time | 43.83 seconds |
| Started | Sep 24 08:12:14 PM UTC 24 |
| Finished | Sep 24 08:12:59 PM UTC 24 |
| Peak memory | 250944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623314997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2623314997 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.2191667312 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 31298190353 ps |
| CPU time | 418.04 seconds |
| Started | Sep 24 08:11:41 PM UTC 24 |
| Finished | Sep 24 08:18:45 PM UTC 24 |
| Peak memory | 582652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191667312 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2191667312 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.3018302818 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 3735656165 ps |
| CPU time | 54.71 seconds |
| Started | Sep 24 08:11:29 PM UTC 24 |
| Finished | Sep 24 08:12:25 PM UTC 24 |
| Peak memory | 234224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018302818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3018302818 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.2173631936 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 21600946187 ps |
| CPU time | 761.18 seconds |
| Started | Sep 24 08:12:42 PM UTC 24 |
| Finished | Sep 24 08:25:33 PM UTC 24 |
| Peak memory | 539740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173631936 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2173631936 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all_with_rand_reset.603448227 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12438209728 ps |
| CPU time | 213.75 seconds |
| Started | Sep 24 08:12:42 PM UTC 24 |
| Finished | Sep 24 08:16:19 PM UTC 24 |
| Peak memory | 308104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=603448227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_w ith_rand_reset.603448227 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.749297848 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 13997104 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:14:17 PM UTC 24 |
| Finished | Sep 24 08:14:19 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749297848 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.749297848 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.1269105567 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1801039369 ps |
| CPU time | 96.78 seconds |
| Started | Sep 24 08:13:02 PM UTC 24 |
| Finished | Sep 24 08:14:41 PM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269105567 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1269105567 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.386517533 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 5448870590 ps |
| CPU time | 260.03 seconds |
| Started | Sep 24 08:12:45 PM UTC 24 |
| Finished | Sep 24 08:17:09 PM UTC 24 |
| Peak memory | 238616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386517533 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.386517533 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.1681623862 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 667797844 ps |
| CPU time | 16.54 seconds |
| Started | Sep 24 08:13:39 PM UTC 24 |
| Finished | Sep 24 08:13:57 PM UTC 24 |
| Peak memory | 233412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681623862 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1681623862 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.3045346678 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1419844593 ps |
| CPU time | 33.87 seconds |
| Started | Sep 24 08:13:46 PM UTC 24 |
| Finished | Sep 24 08:14:22 PM UTC 24 |
| Peak memory | 234092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045346678 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3045346678 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.1033096759 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8328233007 ps |
| CPU time | 40.52 seconds |
| Started | Sep 24 08:13:55 PM UTC 24 |
| Finished | Sep 24 08:14:37 PM UTC 24 |
| Peak memory | 234276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033096759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1033096759 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.1479218286 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 32255692283 ps |
| CPU time | 298.11 seconds |
| Started | Sep 24 08:13:03 PM UTC 24 |
| Finished | Sep 24 08:18:06 PM UTC 24 |
| Peak memory | 455676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479218286 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.1479218286 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.637964860 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4840737097 ps |
| CPU time | 255.48 seconds |
| Started | Sep 24 08:13:27 PM UTC 24 |
| Finished | Sep 24 08:17:47 PM UTC 24 |
| Peak memory | 316252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637964860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.637964860 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.2534627040 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 360439387 ps |
| CPU time | 4.87 seconds |
| Started | Sep 24 08:13:32 PM UTC 24 |
| Finished | Sep 24 08:13:38 PM UTC 24 |
| Peak memory | 227208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534627040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2534627040 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.1092285863 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 187085126 ps |
| CPU time | 3 seconds |
| Started | Sep 24 08:13:58 PM UTC 24 |
| Finished | Sep 24 08:14:02 PM UTC 24 |
| Peak memory | 229664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092285863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1092285863 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.446511220 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 89904225708 ps |
| CPU time | 4126.87 seconds |
| Started | Sep 24 08:12:43 PM UTC 24 |
| Finished | Sep 24 09:22:17 PM UTC 24 |
| Peak memory | 4346772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446511220 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.446511220 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.1558967533 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 5092395763 ps |
| CPU time | 143.43 seconds |
| Started | Sep 24 08:13:11 PM UTC 24 |
| Finished | Sep 24 08:15:37 PM UTC 24 |
| Peak memory | 285860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558967533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1558967533 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.2584826894 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3310287267 ps |
| CPU time | 146.02 seconds |
| Started | Sep 24 08:12:45 PM UTC 24 |
| Finished | Sep 24 08:15:14 PM UTC 24 |
| Peak memory | 289520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584826894 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2584826894 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.3447860522 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3857609661 ps |
| CPU time | 25.12 seconds |
| Started | Sep 24 08:12:43 PM UTC 24 |
| Finished | Sep 24 08:13:10 PM UTC 24 |
| Peak memory | 231716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447860522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3447860522 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.3201479922 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 76968064590 ps |
| CPU time | 2260.78 seconds |
| Started | Sep 24 08:14:00 PM UTC 24 |
| Finished | Sep 24 08:52:08 PM UTC 24 |
| Peak memory | 1496480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep o/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201479922 -assert nopo stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3201479922 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |