Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42880375	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

52213674

1

T1

545

T2

435

T3

697

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51099733	1			T1	431		T2	339		T3	796
values[0x0]	21337643	1			T1	183		T2	162		T3	201
values[0x1]	22656673	1			T1	202		T2	158		T3	226

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33304023	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

61790026

1

T1

598

T2

473

T3

837

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	387104	1			T1	5		T2	8		T3	14
valid_sources[0x01]	298769	1			T1	2		T2	2		T3	3
valid_sources[0x02]	297132	1			T1	4		T2	1		T3	7
valid_sources[0x03]	299132	1			T1	3		T2	1		T12	3
valid_sources[0x04]	299318	1			T1	3		T2	1		T3	6
valid_sources[0x05]	299350	1			T1	4		T3	2		T4	6
valid_sources[0x06]	296643	1			T1	10		T2	1		T3	9
valid_sources[0x07]	298363	1			T1	2		T2	2		T3	7
valid_sources[0x08]	544623	1			T1	2		T3	2		T13	71
valid_sources[0x09]	295454	1			T1	3		T3	3		T12	2
valid_sources[0x0a]	306716	1			T1	1		T2	3		T3	13
valid_sources[0x0b]	449269	1			T1	2		T3	2		T4	1
valid_sources[0x0c]	300512	1			T1	1		T2	2		T3	5
valid_sources[0x0d]	296379	1			T1	4		T3	1		T12	2
valid_sources[0x0e]	413681	1			T1	4		T2	3		T3	15
valid_sources[0x0f]	297542	1			T1	3		T2	7		T3	4
valid_sources[0x10]	399919	1			T1	2		T2	3		T3	11
valid_sources[0x11]	325562	1			T1	1		T3	2		T4	5
valid_sources[0x12]	294118	1			T1	4		T2	3		T3	2
valid_sources[0x13]	329073	1			T1	6		T2	1		T3	8
valid_sources[0x14]	746976	1			T1	8		T3	1		T4	6
valid_sources[0x15]	298437	1			T1	6		T2	1		T3	4
valid_sources[0x16]	530951	1			T1	3		T2	6		T3	5
valid_sources[0x17]	296450	1			T1	5		T3	2		T4	2
valid_sources[0x18]	316782	1			T1	3		T3	7		T4	2
valid_sources[0x19]	300609	1			T1	3		T2	3		T3	7
valid_sources[0x1a]	301889	1			T1	4		T3	6		T12	1
valid_sources[0x1b]	297696	1			T1	7		T2	2		T3	2
valid_sources[0x1c]	1453641	1			T1	6		T2	1		T3	2
valid_sources[0x1d]	301580	1			T1	5		T4	1		T12	2
valid_sources[0x1e]	294742	1			T1	5		T2	3		T3	9
valid_sources[0x1f]	498107	1			T1	5		T2	1		T3	6
valid_sources[0x20]	297507	1			T1	2		T2	6		T3	4
valid_sources[0x21]	312100	1			T1	4		T3	5		T12	3
valid_sources[0x22]	316206	1			T1	2		T2	2		T3	4
valid_sources[0x23]	302400	1			T1	2		T2	1		T3	4
valid_sources[0x24]	298609	1			T1	5		T3	6		T4	3
valid_sources[0x25]	295013	1			T1	3		T2	5		T3	8
valid_sources[0x26]	438135	1			T1	1		T3	4		T12	2
valid_sources[0x27]	293476	1			T1	5		T2	2		T3	4
valid_sources[0x28]	366540	1			T1	3		T2	5		T3	15
valid_sources[0x29]	300261	1			T1	7		T2	1		T12	2
valid_sources[0x2a]	396616	1			T1	3		T2	1		T3	9
valid_sources[0x2b]	296806	1			T1	3		T2	3		T3	1
valid_sources[0x2c]	1152323	1			T1	1		T3	10		T4	3
valid_sources[0x2d]	355528	1			T1	2		T2	2		T3	4
valid_sources[0x2e]	322341	1			T1	5		T2	1		T3	16
valid_sources[0x2f]	461244	1			T1	6		T3	3		T12	3
valid_sources[0x30]	297617	1			T1	3		T2	17		T3	1
valid_sources[0x31]	418945	1			T1	3		T2	3		T3	1
valid_sources[0x32]	1191975	1			T1	3		T2	6		T3	5
valid_sources[0x33]	317865	1			T1	6		T2	9		T3	6
valid_sources[0x34]	354590	1			T1	2		T2	2		T3	7
valid_sources[0x35]	304297	1			T1	3		T2	1		T3	5
valid_sources[0x36]	445328	1			T1	4		T2	2		T3	4
valid_sources[0x37]	387257	1			T1	2		T3	2		T12	1
valid_sources[0x38]	306348	1			T1	2		T3	3		T12	4
valid_sources[0x39]	422628	1			T1	5		T2	1		T3	2
valid_sources[0x3a]	294108	1			T1	2		T3	1		T13	66
valid_sources[0x3b]	298650	1			T1	2		T2	3		T12	2
valid_sources[0x3c]	519633	1			T1	4		T3	4		T12	4
valid_sources[0x3d]	297124	1			T1	5		T2	5		T3	4
valid_sources[0x3e]	299627	1			T1	4		T2	4		T3	6
valid_sources[0x3f]	296439	1			T1	1		T3	2		T12	2
valid_sources[0x40]	293326	1			T1	4		T2	2		T3	4
valid_sources[0x41]	726406	1			T1	2		T2	1		T3	4
valid_sources[0x42]	335412	1			T1	3		T3	4		T12	2
valid_sources[0x43]	320812	1			T1	2		T2	5		T3	11
valid_sources[0x44]	395788	1			T1	2		T3	4		T12	1
valid_sources[0x45]	321565	1			T1	3		T2	4		T3	10
valid_sources[0x46]	296246	1			T1	2		T2	4		T3	4
valid_sources[0x47]	341810	1			T1	3		T2	2		T3	6
valid_sources[0x48]	385079	1			T1	1		T2	2		T3	2
valid_sources[0x49]	300133	1			T1	1		T2	5		T3	5
valid_sources[0x4a]	296851	1			T1	3		T2	15		T4	2
valid_sources[0x4b]	295263	1			T1	2		T3	10		T4	6
valid_sources[0x4c]	296050	1			T1	2		T2	11		T3	6
valid_sources[0x4d]	301149	1			T1	1		T3	5		T12	5
valid_sources[0x4e]	299673	1			T1	2		T2	4		T3	6
valid_sources[0x4f]	294620	1			T1	3		T2	3		T3	3
valid_sources[0x50]	301790	1			T1	5		T3	6		T12	1
valid_sources[0x51]	298695	1			T1	3		T3	8		T12	1
valid_sources[0x52]	309497	1			T1	1		T2	2		T3	2
valid_sources[0x53]	300353	1			T1	3		T2	1		T3	3
valid_sources[0x54]	298188	1			T1	1		T2	3		T3	3
valid_sources[0x55]	295737	1			T1	2		T2	2		T3	2
valid_sources[0x56]	299185	1			T1	3		T2	7		T3	3
valid_sources[0x57]	299456	1			T1	3		T2	2		T3	5
valid_sources[0x58]	308030	1			T1	5		T2	5		T3	2
valid_sources[0x59]	744768	1			T1	1		T2	3		T3	1
valid_sources[0x5a]	297392	1			T1	3		T2	2		T3	4
valid_sources[0x5b]	295333	1			T1	5		T2	6		T3	1
valid_sources[0x5c]	299848	1			T2	2		T3	5		T12	1
valid_sources[0x5d]	295964	1			T1	8		T3	4		T12	4
valid_sources[0x5e]	400243	1			T1	2		T2	6		T3	7
valid_sources[0x5f]	298465	1			T1	1		T2	1		T3	3
valid_sources[0x60]	294819	1			T1	1		T2	4		T12	2
valid_sources[0x61]	297107	1			T1	7		T2	2		T3	10
valid_sources[0x62]	302906	1			T1	3		T2	2		T3	6
valid_sources[0x63]	368840	1			T1	4		T2	1		T3	2
valid_sources[0x64]	300297	1			T1	5		T2	6		T3	7
valid_sources[0x65]	323147	1			T1	5		T2	2		T3	6
valid_sources[0x66]	292889	1			T1	1		T2	3		T3	4
valid_sources[0x67]	553120	1			T1	1		T2	1		T3	10
valid_sources[0x68]	427608	1			T1	3		T3	4		T12	2
valid_sources[0x69]	298757	1			T1	1		T2	3		T3	7
valid_sources[0x6a]	298852	1			T1	3		T2	11		T3	13
valid_sources[0x6b]	324667	1			T1	6		T3	2		T12	3
valid_sources[0x6c]	302916	1			T1	4		T2	1		T3	8
valid_sources[0x6d]	292229	1			T1	4		T2	1		T3	4
valid_sources[0x6e]	297253	1			T1	1		T2	5		T3	4
valid_sources[0x6f]	328404	1			T1	3		T2	1		T3	4
valid_sources[0x70]	296390	1			T1	1		T2	5		T3	7
valid_sources[0x71]	295603	1			T1	2		T2	3		T3	4
valid_sources[0x72]	300606	1			T1	3		T2	1		T3	7
valid_sources[0x73]	858690	1			T1	3		T2	2		T3	4
valid_sources[0x74]	299031	1			T1	7		T2	2		T3	1
valid_sources[0x75]	299705	1			T2	2		T3	2		T12	3
valid_sources[0x76]	299887	1			T1	2		T2	4		T3	6
valid_sources[0x77]	293844	1			T1	4		T3	1		T12	3
valid_sources[0x78]	298307	1			T1	1		T2	4		T3	10
valid_sources[0x79]	742547	1			T1	4		T3	5		T12	1
valid_sources[0x7a]	296257	1			T1	2		T2	1		T3	5
valid_sources[0x7b]	296854	1			T1	2		T2	3		T3	5
valid_sources[0x7c]	296099	1			T1	5		T2	2		T3	2
valid_sources[0x7d]	1102647	1			T1	1		T3	1		T12	2
valid_sources[0x7e]	673950	1			T1	3		T2	5		T3	2
valid_sources[0x7f]	294333	1			T1	2		T2	5		T3	14
valid_sources[0x80]	296975	1			T1	5		T3	3		T12	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24660474

1

T1

269

T2

220

T3

484

values[0x0]

all_enables

biggest_size

14471532

1

T1

141

T2

116

T3

117

values[0x1]

all_enables

biggest_size

13081668

1

T1

135

T2

99

T3

96