Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42936337

1

T1

271

T2

224

T3

526

full_word

52217145

1

T1

545

T2

435

T3

697

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	95153162	1			T1	816		T2	659		T3	1223
auto[TlIntgErrCmd]	97	1			T121	7		T122	4		T123	6
auto[TlIntgErrData]	115	1			T121	6		T122	4		T123	7
auto[TlIntgErrBoth]	108	1			T121	7		T122	2		T123	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51113420

1

T1

431

T2

339

T3

796

auto[1]

44040062

1

T1

385

T2

320

T3

427

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26451779	1			T1	162		T2	119		T3	312
auto[TlIntgErrNone]	partial	auto[1]	16484262	1			T1	109		T2	105		T3	214
auto[TlIntgErrNone]	full_word	auto[0]	24661504	1			T1	269		T2	220		T3	484
auto[TlIntgErrNone]	full_word	auto[1]	27555617	1			T1	276		T2	215		T3	213
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T121	1		T122	2		T123	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T121	5		T122	2		T123	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T175	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T121	1		T176	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T121	3		T122	3		T123	5
auto[TlIntgErrData]	partial	auto[1]	49	1			T121	2		T122	1		T123	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T121	1		T177	1		T178	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T179	1		T177	1		T178	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T121	1		T122	1		T123	1
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T121	6		T122	1		T123	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T180	1		T181	1		T178	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T174	1		T172	1		T178	1